利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

12 条记录 (耗时 0.052 秒)

    Method for automatically generating checkers for finding functional defects in a description of a circuit
    3.
    发明授权
    Method for automatically generating checkers for finding functional defects in a description of a circuit 有权
    一种用于自动生成检查器以查找电路描述中的功能缺陷的方法

    公开(公告)号：US06609229B1

    公开(公告)日：2003-08-19

    申请号：US09635598

    申请日：2000-08-09

    申请人： Tai An Ly ,  Jean-Charles Giomi ,  Kalyana C. Mulam ,  Paul Andrew Wilcox ,  David Lansing Dill ,  Paul Estrada, II ,  Chian-Min Richard Ho ,  Jing Chyuarn Lin ,  Robert Kristianto Mardjuki ,  Lawrence Curtis Widdoes, Jr. ,  Ping Fai Yeung

    发明人： Tai An Ly ,  Jean-Charles Giomi ,  Kalyana C. Mulam ,  Paul Andrew Wilcox ,  David Lansing Dill ,  Paul Estrada, II ,  Chian-Min Richard Ho ,  Jing Chyuarn Lin ,  Robert Kristianto Mardjuki ,  Lawrence Curtis Widdoes, Jr. ,  Ping Fai Yeung

    IPC分类号： G06F1750

    CPC分类号： G06F17/5022

    摘要： A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging detective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers. Some of the checkers may use signals generated by other checkers.

    摘要翻译： 编程的计算机产生标记正在进行功能验证的电路的描述中的功能缺陷的电路（称为“检查器”）的描述。 编程的计算机自动将电路的描述转换为图形，自动检查图表中预定布置的节点和连接的实例，并自动生成指示，该指令根据已知的缺陷行为标记由实例表示的设备的行为。 在仿真或模拟电路期间或在半导体管芯中的电路操作期间可以使用检查器。电路的描述可以在Verilog或VHDL中，自动生成的检查器也可以在Verilog或VHDL中描述。 因此，检查器可以与电路共同模拟，监测电路的仿真操作和标记检测行为。 编程的计算机可以自动确定电路中寄存器的负载条件，并自动生成检查器以标志寄存器中的数据丢失。 一些检查者可能会使用其他检查器产生的信号。

    Method for automatically generating checkers for finding functional defects in a description of a circuit
    6.
    发明授权
    Method for automatically generating checkers for finding functional defects in a description of a circuit 失效
    一种用于自动生成检查器以查找电路描述中的功能缺陷的方法

    公开(公告)号：US06175946B1

    公开(公告)日：2001-01-16

    申请号：US08955329

    申请日：1997-10-20

    申请人： Tai An Ly ,  Jean-Charles Giomi ,  Kalyana C. Mulam ,  Paul Andrew Wilcox ,  David Lansing Dill ,  Paul Estrada, II ,  Chian-Min Richard Ho ,  Jing Chyuarn Lin ,  Robert Kristianto Mardjuki ,  Lawrence Curtis Widdoes, Jr. ,  Ping Fai Yeung

    发明人： Tai An Ly ,  Jean-Charles Giomi ,  Kalyana C. Mulam ,  Paul Andrew Wilcox ,  David Lansing Dill ,  Paul Estrada, II ,  Chian-Min Richard Ho ,  Jing Chyuarn Lin ,  Robert Kristianto Mardjuki ,  Lawrence Curtis Widdoes, Jr. ,  Ping Fai Yeung

    IPC分类号： G06F1750

    CPC分类号： G06F17/5022

    摘要： A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers. Some of the checkers may use signals generated by other checkers.

    摘要翻译： 编程的计算机产生标记正在进行功能验证的电路的描述中的功能缺陷的电路（称为“检查器”）的描述。 编程的计算机自动将电路的描述转换为图形，自动检查图表中预定布置的节点和连接的实例，并自动生成指示，该指令根据已知的缺陷行为标记由实例表示的设备的行为。 可以在仿真或模拟电路期间或在半导体管芯中的电路操作期间使用检查器。 电路的描述可以在Verilog或VHDL中，自动生成的检查器也可以在Verilog或VHDL中描述。 因此，检查器可以与电路共同模拟，监视电路的模拟操作并标记有缺陷的行为。 编程的计算机可以自动确定电路中寄存器的负载条件，并自动生成检查器以标志寄存器中的数据丢失。 一些检查者可能会使用其他检查器产生的信号。

    Metastability injector for a circuit description
    7.
    发明授权
    Metastability injector for a circuit description 有权
    Metastability注射器用于电路描述

    公开(公告)号：US07243322B1

    公开(公告)日：2007-07-10

    申请号：US10859055

    申请日：2004-06-01

    申请人： Tai An Ly ,  Ka Kei Kwok ,  Vijaya Vardhan Gupta ,  Ross Andrew Ander ,  Ping Fai Yeung ,  Neil Patrick Hand ,  Lawrence Curtis Widdoes, Jr.

    发明人： Tai An Ly ,  Ka Kei Kwok ,  Vijaya Vardhan Gupta ,  Ross Andrew Ander ,  Ping Fai Yeung ,  Neil Patrick Hand ,  Lawrence Curtis Widdoes, Jr.

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5022 ,  G01R31/30

    摘要： During verification of a description of a circuit containing a pre-determined assertion, in order to detect incorrect behavior of the circuit that may be caused by metastability occurring in signals that cross clock domains (“CDC” signals) in the circuit, the description of the circuit is automatically transformed by addition of circuitry to inject the effects of metastability into the CDC signals. The transformed description containing the circuitry to inject metastability is verified in the normal manner. Certain embodiments analyze the transformed description using a model checking method to determine a stimulus sequence that will cause the pre-determined assertion to be violated. The transformed circuit is then simulated in some embodiments, using the stimulus sequence from model checking, and an incorrect behavior of the circuit due to metastability is displayed, for diagnosis by the circuit designer. The circuit designer may revise the circuit description and iterate as noted above.

    摘要翻译： 在验证包含预定断言的电路的描述期间，为了检测可能由在电路中交叉时钟域（“CDC”信号）的信号中发生的亚稳态引起的电路的不正确行为，描述 该电路通过添加电路自动转换，以将亚稳态的影响注入到CDC信号中。 以正常方式验证包含注入亚稳态的电路的变换描述。 某些实施例使用模型检查方法分析变换的描述，以确定将导致预定的断言被违反的刺激序列。 在一些实施例中，使用来自模型检查的刺激序列来模拟变换电路，并且显示由于亚稳态引起的电路的错误行为，以供电路设计者进行诊断。 电路设计者可以修改电路描述并如上所述进行迭代。

    Metastability injector for a circuit description
    8.
    发明授权
    Metastability injector for a circuit description 有权
    Metastability注射器用于电路描述

    公开(公告)号：US07454728B2

    公开(公告)日：2008-11-18

    申请号：US11759888

    申请日：2007-06-07

    申请人： Tai An Ly ,  Ka Kei Kwok ,  Vijaya Vardhan Gupta ,  Ross Andrew Andersen ,  Ping Fai Yeung ,  Neil Patrick Hand ,  Lawrence Curtis Widdoes, Jr.

    发明人： Tai An Ly ,  Ka Kei Kwok ,  Vijaya Vardhan Gupta ,  Ross Andrew Andersen ,  Ping Fai Yeung ,  Neil Patrick Hand ,  Lawrence Curtis Widdoes, Jr.

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5022 ,  G01R31/30

    摘要： During verification of a description of a circuit containing a pre-determined assertion, in order to detect incorrect behavior of the circuit that may be caused by metastability occurring in signals that cross clock domains (“CDC” signals) in the circuit, the description of the circuit is automatically transformed by addition of circuitry to inject the effects of metastability into the CDC signals. The transformed description containing the circuitry to inject metastability is verified in the normal manner. Certain embodiments analyze the transformed description using a model checking method to determine a stimulus sequence that will cause the pre-determined assertion to be violated. The transformed circuit is then simulated in some embodiments, using the stimulus sequence from model checking, and an incorrect behavior of the circuit due to metastability is displayed, for diagnosis by the circuit designer. The circuit designer may revise the circuit description and iterate as noted above.

    摘要翻译： 在验证包含预定断言的电路的描述期间，为了检测可能由在电路中交叉时钟域（“CDC”信号）的信号中发生的亚稳态引起的电路的不正确行为，描述 该电路通过添加电路自动转换，以将亚稳态的影响注入到CDC信号中。 以正常方式验证包含注入亚稳态的电路的变换描述。 某些实施例使用模型检查方法分析变换的描述，以确定将导致预定的断言被违反的刺激序列。 在一些实施例中，使用来自模型检查的刺激序列来模拟变换电路，并且显示由于亚稳态引起的电路的错误行为，以供电路设计者进行诊断。 电路设计者可以修改电路描述并如上所述进行迭代。

    Metastability effects simulation for a circuit description
    10.
    发明授权
    Metastability effects simulation for a circuit description 有权
    电路描述的均衡性效应模拟

    公开(公告)号：US08438516B2

    公开(公告)日：2013-05-07

    申请号：US12773462

    申请日：2010-05-04

    申请人： Tai An Ly ,  Ka Kei Kwok ,  Vijaya Vardhan Gupta ,  Lawrence Curtis Widdoes, Jr.

    发明人： Tai An Ly ,  Ka Kei Kwok ,  Vijaya Vardhan Gupta ,  Lawrence Curtis Widdoes, Jr.

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/5031 ,  G01R31/30 ,  G06F17/5022

    摘要： A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.

    摘要翻译： 包含至少两个时钟域的电路设计使用用于注入亚稳态效应的新型系统和方法进行模拟。 该系统包括检测器，用于在仿真期间当发送时钟域中的时钟和接收时钟域中的时钟对准时以及当接收时钟域交叉信号的寄存器的输入正在改变时进行检测。 该系统包括覆盖监测器，用于在模拟期间测量与亚稳态注入相关的统计。 在仿真期间的适当时间，系统准确地模拟亚稳态的影响，接收时域交叉信号的寄存器的伪随机反转输出。 通过准确地模拟亚稳态的影响，可以在模拟预先存在的模拟测试的同时检测电路设计中的误差。 具有亚稳态效应注入的模拟是可重复的，不需要修改预先存在的RTL设计文件或模拟测试文件。