公开(公告)号：US08405441B2

公开(公告)日：2013-03-26

申请号：US13070868

申请日：2011-03-24

申请人： Chien-Kuo Su ,  Yi-Tzu Chen ,  Chung-Cheng Chou

发明人： Chien-Kuo Su ,  Yi-Tzu Chen ,  Chung-Cheng Chou

IPC分类号： H03K3/356

CPC分类号： H03K3/012 ,  H03K3/356121 ,  H03K3/356173

摘要： A latch circuit includes an output driver electrically coupled with a circuit. The circuit is electrically coupled with the output driver through a first path and a second path. The circuit is configured to receive a data signal. The circuit is configured to divert a signal of the output driver through the first path at a falling edge of the data signal. The circuit is configured to divert the signal of the output driver through the second path at a rising edge of the data signal.

摘要翻译： 锁存电路包括与电路电耦合的输出驱动器。 电路通过第一路径和第二路径与输出驱动器电耦合。 电路被配置为接收数据信号。 电路被配置为在数据信号的下降沿通过第一路径转移输出驱动器的信号。 电路被配置为在数据信号的上升沿通过第二路径转移输出驱动器的信号。

公开(公告)号：US09064550B2

公开(公告)日：2015-06-23

申请号：US13279375

申请日：2011-10-24

申请人： Jonathan Tsung-Yung Chang ,  Chiting Cheng ,  Chien-Kuo Su ,  Chung-Cheng Chou ,  Jack Liu

发明人： Jonathan Tsung-Yung Chang ,  Chiting Cheng ,  Chien-Kuo Su ,  Chung-Cheng Chou ,  Jack Liu

IPC分类号： G11C11/00 ,  G11C8/08 ,  G11C11/418

CPC分类号： G11C8/08 ,  G11C11/418

摘要： A memory access operation on a bit cell of a digital memory, e.g., a static random access memory (SRAM), is assisted by reducing the word line control voltage for reading and boosting it for writing, thus improving data integrity. The bit cell has cross coupled inverters for storing and retrieving a logic state via bit line connections through a passing gate transistor controlled by the word line. A level of a word line signal controlling the passing gate transistor is shifted from a first voltage value to a higher second voltage value to begin a memory access cycle. The level of the word line signal is shifted from the second voltage value to a third voltage value less than the second voltage value during the access cycle. The word line signal is maintained at the third voltage value for a time interval during the access cycle.

摘要翻译： 数字存储器的位单元（例如静态随机存取存储器（SRAM））上的存储器访问操作通过减少字线控制电压来进行辅助，用于读取和提升其用于写入，从而提高数据完整性。 位单元具有交叉耦合的反相器，用于经由位线连接通过由字线控制的通过栅极晶体管来存储和取回逻辑状态。 控制通过栅极晶体管的字线信号的电平从第一电压值移位到较高的第二电压值，以开始存储器访问周期。 在访问周期期间，字线信号的电平从第二电压值移位到小于第二电压值的第三电压值。 在访问周期期间，字线信号保持在第三电压值一段时间间隔。