公开(公告)号：US06291260B1

公开(公告)日：2001-09-18

申请号：US09482758

申请日：2000-01-13

申请人： Chien-Ping Huang ,  April Chen ,  Tzong-Dar Her

发明人： Chien-Ping Huang ,  April Chen ,  Tzong-Dar Her

IPC分类号： H01L2144

CPC分类号： H01L21/481 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

摘要： A crack-preventive substrate for fabricating a solder mask in a device site region includes a substrate, which has a top surface and a bottom surface, and a solder mask layer. The substrate is divided into a device site region and a periphery region. The solder mask layer, disposed on the top surface and bottom surface of the substrate, forms a bare area on the top surface and bottom surface of the substrate by exposing a portion of the substrate on the top surface and bottom surface of the substrate. And the bare areas divide the solder mask layer into a “device site region solder mask layer” and a “periphery region solder mask layer”. As a result, the crack lines generated on the solder mask layer at the perimeter of the substrate will not develop toward the solder mask in the device site region.

摘要翻译： 用于在器件位置区域制造焊料掩模的防裂衬底包括具有顶表面和底表面的衬底和焊料掩模层。 将基板分为装置位置区域和外围区域。 设置在基板的顶表面和底表面上的焊料掩模层通过在基板的顶表面和底表面上暴露基板的一部分而在基板的顶表面和底表面上形成裸露区域。 并且裸露区域将焊接掩模层分成“器件区域焊料掩模层”和“外围区域焊接掩模层”。 结果，在衬底的周边处的焊料掩模层上产生的裂纹线将不会朝向器件位置区域中的焊接掩模发展。

公开(公告)号：US06392425B1

公开(公告)日：2002-05-21

申请号：US09475005

申请日：1999-12-30

申请人： April Chen ,  Chih-Chin Liao ,  Tzong-Dar Her

发明人： April Chen ,  Chih-Chin Liao ,  Tzong-Dar Her

IPC分类号： G01R3102

CPC分类号： G01R1/0483 ,  H01L2224/48463 ,  H01L2224/85181

摘要： A multi-chip packaging substrate having a non-sticking test structure consists of a plurality of non-sticking test spots formed in the periphery zone outside the chip-packaging zone of a multi-chip packaging substrate. Each of these non-sticking test spots is electrically connected to an adjacent one of a plurality of chip pads respectively in the chip packaging zone through a plurality of conductive traces while there are no electrical connections connected one another among the chip pads.

摘要翻译： 具有不粘试验结构的多芯片封装基板由在多芯片封装基板的芯片封装区域外部的外围区域形成的多个不粘附试验点构成。 这些不粘贴的测试点中的每一个都通过多个导电迹线电连接到芯片封装区域中的多个芯片焊盘中的相邻的一个，同时在芯片焊盘之间没有彼此连接的电连接。