公开(公告)号：US08461675B2

公开(公告)日：2013-06-11

申请号：US11301715

申请日：2005-12-13

Applicant: Hem Takiar ,  Ken Jian Ming Wang ,  Chih-Chin Liao ,  Han-Shiao Chen

Inventor： Hem Takiar ,  Ken Jian Ming Wang ,  Chih-Chin Liao ,  Han-Shiao Chen

IPC: H01L23/52 ,  H01L23/48

CPC classification number: H05K3/242 ,  H01L21/4846 ,  H01L23/49838 ,  H01L24/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H05K3/0052 ,  H05K2201/09263 ,  H01L2924/00

Abstract: A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.

Abstract translation: 公开了半导体管芯衬底面板，其包括在面板上相邻的半导体封装轮廓之间的最小间隙宽度，同时确保电镀电端子的电隔离。 通过减小相邻封装轮廓之间的边界的宽度，在用于半导体封装的衬底面板上获得额外的空间。

公开(公告)号：US08129272B2

公开(公告)日：2012-03-06

申请号：US12493582

申请日：2009-06-29

Applicant: Hem Takiar ,  Cheeman Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

Inventor： Hem Takiar ,  Cheeman Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

IPC: H01L21/44

CPC classification number: H01L25/0657 ,  H01L21/3205 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/5386 ,  H01L24/48 ,  H01L24/64 ,  H01L24/65 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

Abstract translation: 公开了一种加强的半导体管芯基板和封装。 衬底可以包括形成有非线性边缘的接触指状物。 向接触指边缘提供非线性轮廓减少了施加在半导体管芯上的机械应力，否则这些应力将以直接接触指的边缘发生。 衬底可以附加地或可选地包括从接触指一定角度延伸的电镀迹线。 以一定角度延伸，至少衬底边缘处的电镀迹线的端部被覆盖在半导体封装被封装的盖子的下方。 因此，当与主机设备一起使用时，避免了盖子下方的电镀痕迹的端部和主机设备的接触销之间的接触。

公开(公告)号：US20120025396A1

公开(公告)日：2012-02-02

申请号：US12844959

申请日：2010-07-28

Applicant: Chih-Chin Liao ,  Cheeman Yu ,  Ya Huei Lee

Inventor： Chih-Chin Liao ,  Cheeman Yu ,  Ya Huei Lee

IPC: H01L23/488

CPC classification number: H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85207 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor die package is disclosed. An example of the semiconductor package includes a first group of semiconductor die interspersed with a second group of semiconductor die. The die from the first and second groups are offset from each other along a first axis and staggered with respect to each other along a second axis orthogonal to the first axis. A second example of the semiconductor package includes an irregular shaped edge and a wire bond to the substrate from a semiconductor die above the lowermost semiconductor die in the package.

Abstract translation: 公开了一种半导体管芯封装。 半导体封装的示例包括散布有第二组半导体管芯的第一组半导体管芯。 来自第一组和第二组的模具沿着第一轴线彼此偏移并且沿着与第一轴线正交的第二轴线相对于彼此交错。 半导体封装的第二示例包括不规则形状的边缘和从封装中的最低半导体管芯上方的半导体管芯到基板的引线接合。

公开(公告)号：US08097495B2

公开(公告)日：2012-01-17

申请号：US12060418

申请日：2008-04-01

Applicant: Ming Hsun Lee ,  Chih-Chin Liao ,  Cheemen Yu ,  Hem Takiar

Inventor： Ming Hsun Lee ,  Chih-Chin Liao ,  Cheemen Yu ,  Hem Takiar

IPC: H01L21/50 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L23/4951 ,  H01L23/49551 ,  H01L23/49558 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A leadframe for a semiconductor package is disclosed including electrical leads which extend from one side of the leadframe to an opposite side of the leadframe, where electrical connection may be made with the semiconductor die at the second side of the leadframe. The semiconductor die may be supported on the leads extending across the leadframe. The package may further include a spacer layer affixed to the electrical leads to fortify the semiconductor package and to prevent exposure of the electrical leads during the molding of the package.

Abstract translation: 公开了一种用于半导体封装的引线框架，其包括从引线框架的一侧延伸到引线框架的相反侧的电引线，其中可以在引线框架的第二侧与半导体管芯进行电连接。 半导体管芯可以被支撑在引导框架上延伸的引线上。 封装还可以包括固定到电引线上的间隔层，以强化半导体封装并防止在封装成型期间电引线的暴露。

公开(公告)号：US08053880B2

公开(公告)日：2011-11-08

申请号：US12489298

申请日：2009-06-22

Applicant: Cheeman Yu ,  Chih-Chin Liao ,  Hem Takiar

Inventor： Cheeman Yu ,  Chih-Chin Liao ,  Hem Takiar

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L24/73 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.

Abstract translation: 公开了一种包括多个堆叠的半导体封装的电子部件。 第一个这样的实施例包括用于电耦合堆叠的半导体封装的内部连接器。 第二个这样的实施例包括用于电耦合堆叠的半导体封装的外部连接器。

公开(公告)号：US20090263969A1

公开(公告)日：2009-10-22

申请号：US12493582

申请日：2009-06-29

Applicant: Hem Takiar ,  Cheemen Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

Inventor： Hem Takiar ,  Cheemen Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

IPC: H01L21/3205

CPC classification number: H01L25/0657 ,  H01L21/3205 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/5386 ,  H01L24/48 ,  H01L24/64 ,  H01L24/65 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

Abstract translation: 公开了一种加强的半导体管芯基板和封装。 衬底可以包括形成有非线性边缘的接触指状物。 向接触指边缘提供非线性轮廓减少了施加在半导体管芯上的机械应力，否则这些应力将以直接接触指的边缘发生。 衬底可以附加地或可选地包括从接触指一定角度延伸的电镀迹线。 以一定角度延伸，至少衬底边缘处的电镀迹线的端部被覆盖在半导体封装被封装的盖子的下方。 因此，当与主机设备一起使用时，避免了盖子下方的电镀痕迹的端部和主机设备的接触销之间的接触。

公开(公告)号：US20090065902A1

公开(公告)日：2009-03-12

申请号：US11853428

申请日：2007-09-11

Applicant: Cheemen Yu ,  Chih-Chin Liao ,  Hem Takiar

Inventor： Cheemen Yu ,  Chih-Chin Liao ,  Hem Takiar

IPC: H01L29/06 ,  H01L21/304 ,  H01L21/56

CPC classification number: H01L21/3043 ,  H01L21/78 ,  H01L23/3121 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/97 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method of forming a low profile semiconductor package, and a semiconductor package formed thereby, is disclosed. The semiconductor die is formed with one or more sloped edges on which electrically conductive traces may be deposited to allow the semiconductor die to be coupled to another die and/or a substrate on which the die is mounted. Depositing the electrical traces directly on the surface and sloped edge of the die allows the die to be electrically coupled without bond wires, thereby allowing a reduction in the overall thickness of the package.

Abstract translation: 公开了一种形成低轮廓半导体封装的方法，以及由此形成的半导体封装。 半导体管芯形成有一个或多个倾斜边缘，导电迹线可以沉积在其上，以允许半导体管芯耦合到另一管芯和/或其上安装管芯的衬底。 将电迹线直接沉积在模具的表面和倾斜边缘上，使得模具能够电耦合而没有接合线，从而允许减小包装的整体厚度。

公开(公告)号：US20090004785A1

公开(公告)日：2009-01-01

申请号：US11770078

申请日：2007-06-28

Applicant: Chin-Tien Chiu ,  Hem Takiar ,  Chih-Chin Liao ,  Cheemen Yu ,  Ning Ye ,  Jack Chang Chien

Inventor： Chin-Tien Chiu ,  Hem Takiar ,  Chih-Chin Liao ,  Cheemen Yu ,  Ning Ye ,  Jack Chang Chien

IPC: H01L21/56

CPC classification number: H01L21/56 ,  G06K19/077 ,  H01L23/3121 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A portable memory card and methods of manufacturing same are disclosed. The portable memory includes a substrate having a plurality of holes formed therein. During the encapsulation process, mold compound flows over the top surface of the substrate, through the holes, and down into a recessed section formed in the bottom mold cap plate to form a projection of mold compound on the bottom surface of the substrate.

Abstract translation: 公开了便携式存储卡及其制造方法。 便携式存储器包括其中形成有多个孔的基板。 在封装过程中，模塑料在衬底的顶表面上通过孔流动，并向下流入形成在底模盖板中的凹陷部分，以在基底的底表面上形成模具化合物的突起。

公开(公告)号：US20070267759A1

公开(公告)日：2007-11-22

申请号：US11435518

申请日：2006-05-17

Applicant: Chih-Chin Liao ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Cheemen Yu ,  Hem Takiar

Inventor： Chih-Chin Liao ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Cheemen Yu ,  Hem Takiar

IPC: H01L23/48

CPC classification number: H05K3/243 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K3/28 ,  H05K2201/09781 ,  H05K2201/0989 ,  H01L2924/00

Abstract: A substrate, and a semiconductor die package formed therefrom, are disclosed which include a distributed plating pattern for reducing mechanical stress on the semiconductor die. The substrate according to embodiments of the invention may include traces and contact pads plated in a double image plating process. Additionally, the substrate may include dummy plating areas including plating material. The plated vias and/or traces and the plating material within the dummy plating areas provide a plating pattern which is evenly distributed across the surface of the substrate. The even distribution of the plating pattern prevents peaks and valleys in the finished substrate.

Abstract translation: 公开了一种基板和由其形成的半导体管芯封装，其包括用于减小半导体管芯上的机械应力的分布电镀图案。 根据本发明的实施例的衬底可以包括以双映像电镀工艺电镀的迹线和接触焊盘。 此外，基板可以包括包括电镀材料的虚拟电镀区域。 电镀通孔和/或迹线以及虚拟电镀区域内的电镀材料提供均匀分布在基板表面上的电镀图案。 电镀图案的均匀分布防止成品基板中的峰和谷。

公开(公告)号：US20070132066A1

公开(公告)日：2007-06-14

申请号：US11301715

申请日：2005-12-13

Applicant: Hem Takiar ,  Ken Wang ,  Chih-Chin Liao ,  Han-Shiao Chen

Inventor： Hem Takiar ,  Ken Wang ,  Chih-Chin Liao ,  Han-Shiao Chen

IPC: H01L23/544

CPC classification number: H05K3/242 ,  H01L21/4846 ,  H01L23/49838 ,  H01L24/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H05K3/0052 ,  H05K2201/09263 ,  H01L2924/00

Abstract: A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.

Abstract translation: 公开了半导体管芯衬底面板，其包括在面板上相邻的半导体封装轮廓之间的最小间隙宽度，同时确保电镀电端子的电隔离。 通过减小相邻封装轮廓之间的边界的宽度，在半导体封装的衬底面板上获得额外的空间。