公开(公告)号：US07233276B1

公开(公告)日：2007-06-19

申请号：US11289045

申请日：2005-11-29

Applicant: Chih-haur Huang

Inventor： Chih-haur Huang

IPC: H03M1/34

CPC classification number: H03M1/066 ,  H03M1/145

Abstract: In a pipelined analog to digital converter with multiple stages of sub-converters, capacitor mismatch error can be reduced by splitting the capacitors into multiple numbers and randomly selecting part of the split capacitors as feedback capacitors. The selection of feedback capacitors can be made according to a digital output, clock phase, stage number of the sub-converter or the combination thereof. The approach of the present invention can be applied to the most significant bit (MSB) stage for a pipelined ADC. Moreover, a method for implementing the same is also proposed.

Abstract translation: 在具有多级子转换器的流水线模数转换器中，可以通过将电容器分成多个数字并随机选择部分分离电容器作为反馈电容器来减少电容器失配误差。 可以根据数字输出，时钟相位，子转换器的级数或其组合来进行反馈电容器的选择。 本发明的方法可以应用于流水线ADC的最高有效位（MSB）级。 此外，还提出了一种用于实现该方法的方法。

公开(公告)号：US20070120725A1

公开(公告)日：2007-05-31

申请号：US11289045

申请日：2005-11-29

Applicant: Chih-haur Huang

Inventor： Chih-haur Huang

IPC: H03M1/38

CPC classification number: H03M1/066 ,  H03M1/145

Abstract: In a pipelined analog to digital converter with multiple stages of sub-converters, capacitor mismatch error can be reduced by splitting the capacitors into multiple numbers and randomly selecting part of the split capacitors as feedback capacitors. The selection of feedback capacitors can be made according to a digital output, clock phase, stage number of the sub-converter or the combination thereof. The approach of the present invention can be applied to the most significant bit (MSB) stage for a pipelined ADC. Moreover, a method for implementing the same is also proposed.

Abstract translation: 在具有多级子转换器的流水线模数转换器中，可以通过将电容器分成多个数字并随机选择部分分离电容器作为反馈电容器来减少电容器失配误差。 可以根据数字输出，时钟相位，子转换器的级数或其组合来进行反馈电容器的选择。 本发明的方法可以应用于流水线ADC的最高有效位（MSB）级。 此外，还提出了一种用于实现该方法的方法。