公开(公告)号：US08441053B2

公开(公告)日：2013-05-14

申请号：US12905100

申请日：2010-10-15

Applicant: Hui-Huang Chen ,  Chih-Yuan Chen ,  Chun-Cheng Chen ,  Ching-Ching Tsai ,  Ting-Jyun He ,  Tai-Liang Hsiung

Inventor： Hui-Huang Chen ,  Chih-Yuan Chen ,  Chun-Cheng Chen ,  Ching-Ching Tsai ,  Ting-Jyun He ,  Tai-Liang Hsiung

IPC: H01L27/108 ,  H01L29/94 ,  H01L21/70 ,  G11C11/34 ,  G11C7/00

CPC classification number: H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10802 ,  H01L29/749

Abstract: A vertical capacitor-less DRAM cell is described, including: a source layer having a first conductivity type, a storage layer disposed on the source layer and having a second conductivity type, an active layer disposed on the storage layer and having the first conductivity type, a drain layer disposed on the active layer and having the second conductivity type, an address gate disposed beside the active layer and separated from the same by a first gate dielectric layer, and a storage gate disposed beside the storage layer and separated from the same by a second gate dielectric layer. The DRAM cell can be written by turning on the MOSFET formed by the storage layer, the active layer, the drain layer, the first gate dielectric layer and the address gate to inject carriers into the storage layer from the active layer.

Abstract translation: 描述了一种垂直无电容器DRAM单元，包括：具有第一导电类型的源极层，设置在源极层上并具有第二导电类型的存储层，设置在存储层上并具有第一导电类型的有源层 ，设置在有源层上并具有第二导电类型的漏极层，位于有源层旁边并与第一栅极介电层分离的地址栅极和设置在存储层旁边并与其分离的存储栅极 通过第二栅极介电层。 可以通过打开由存储层，有源层，漏极层，第一栅极介电层和地址栅极形成的MOSFET来写入DRAM单元，以将载流子从活性层注入到存储层中。

公开(公告)号：US20120092925A1

公开(公告)日：2012-04-19

申请号：US12905100

申请日：2010-10-15

Applicant: Hui-Huang Chen ,  Chih-Yuan Chen ,  Chun-Cheng Chen ,  Ching-Ching Tsai ,  Ting-Jyun He ,  Tai-Liang Hsiung

Inventor： Hui-Huang Chen ,  Chih-Yuan Chen ,  Chun-Cheng Chen ,  Ching-Ching Tsai ,  Ting-Jyun He ,  Tai-Liang Hsiung

IPC: G11C11/34 ,  H01L27/088 ,  G11C7/00

CPC classification number: H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10802 ,  H01L29/749

Abstract: A vertical capacitor-less DRAM cell is described, including: a source layer having a first conductivity type, a storage layer disposed on the source layer and having a second conductivity type, an active layer disposed on the storage layer and having the first conductivity type, a drain layer disposed on the active layer and having the second conductivity type, an address gate disposed beside the active layer and separated from the same by a first gate dielectric layer, and a storage gate disposed beside the storage layer and separated from the same by a second gate dielectric layer. The DRAM cell can be written by turning on the MOSFET formed by the storage layer, the active layer, the drain layer, the first gate dielectric layer and the address gate to inject carriers into the storage layer from the active layer.

Abstract translation: 描述了一种垂直无电容器DRAM单元，包括：具有第一导电类型的源极层，设置在源极层上并具有第二导电类型的存储层，设置在存储层上并具有第一导电类型的有源层 ，设置在有源层上并具有第二导电类型的漏极层，位于有源层旁边并与第一栅极介电层分离的地址栅极和设置在存储层旁边并与其分离的存储栅极 通过第二栅极介电层。 可以通过打开由存储层，有源层，漏极层，第一栅极介电层和地址栅极形成的MOSFET来写入DRAM单元，以将载流子从活性层注入到存储层中。

公开(公告)号：US10919140B2

公开(公告)日：2021-02-16

申请号：US16131534

申请日：2018-09-14

Applicant: Ching-Ching Tsai

Inventor： Ching-Ching Tsai

IPC: B25G1/10 ,  B25B15/04 ,  B25B23/16 ,  B25B15/02

Abstract: A handle of a hand tool includes a body made of a first material and a bit is connected to the bottom of the body. A buffering portion made of a second material integrally formed to the outside of the body. The second material has a proper elasticity and is less hard than the first material. A grasp portion made of a third material integrally formed with the buffering portion. The second material is less hard than the third material. The grasp portion has multiple recesses for easily grasp by the user. The buffering portion buffers or absorbs the shifting of the grasp portion to maintain the bit to be perpendicular to the top face of the bolt head so as to effectively drive the bolt.