公开(公告)号：US20050207225A1

公开(公告)日：2005-09-22

申请号：US10803183

申请日：2004-03-17

申请人： Chiou-Feng Chen ,  Caleb Cho ,  Ming-Jer Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

发明人： Chiou-Feng Chen ,  Caleb Cho ,  Ming-Jer Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

IPC分类号： G11C16/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115

CPC分类号： G11C16/0483 ,  G11C2216/04 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

摘要翻译： 自对准分裂栅极NAND闪速存储单元阵列及其制造工艺，其中自对准分裂栅极单元行在衬底的有源区域中的位线扩散与公共源极扩散之间形成。 每个单元具有彼此堆叠和自对准的控制和浮置栅极，并且擦除和选择与层叠栅极分离并与堆叠栅极自对准的栅极，每行的两端的选择栅极部分地重叠位 排列源扩散。 擦除栅极下面的沟道区域是重掺杂的，以减小位线和源极扩散之间的沟道电阻，并且浮置栅极以其它栅极包围，从而提供显着增强的与浮栅的高电压耦合 其他大门。 存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。