公开(公告)号：US08188780B2

公开(公告)日：2012-05-29

申请号：US11648194

申请日：2006-12-29

申请人： Christian Pacha ,  Siegmar Köppe ,  Karl Zapf

发明人： Christian Pacha ,  Siegmar Köppe ,  Karl Zapf

IPC分类号： H03K3/00

CPC分类号： H03K3/35625 ,  H03K3/012

摘要： A pulsed static flip-flop comprises a first logic device which combines a logic signal with a pulsed signal and outputs a set signal, a second logic device which logically combines the logic signal with a complementary pulsed signal and outputs a reset signal; and a latch device comprising storage means which hold a logic hold level to be tapped off as a stored logic state of the logic signal. The logic hold level is adjustable to a first logic level by a first push-pull transistor controlled by the set signal and to a second logic level by a second push-pull transistor controlled by the reset signal.

摘要翻译： 脉冲静态触发器包括将逻辑信号与脉冲信号组合并输出设定信号的第一逻辑器件，将逻辑信号与互补脉冲信号逻辑组合并输出复位信号的第二逻辑器件; 以及锁存装置，其包括存储装置，其保持要作为逻辑信号的存储的逻辑状态被分接的逻辑保持电平。 逻辑保持电平由被设置信号控制的第一推挽晶体调节到第一逻辑电平，并且由复位信号控制的第二推挽晶体调节到第二逻辑电平。

公开(公告)号：US20070182473A1

公开(公告)日：2007-08-09

申请号：US11648194

申请日：2006-12-29

申请人： Christian Pacha ,  Siegmar Koppe ,  Karl Zapf

发明人： Christian Pacha ,  Siegmar Koppe ,  Karl Zapf

IPC分类号： H03K3/00

CPC分类号： H03K3/35625 ,  H03K3/012

摘要： A pulsed static flip-flop comprises a first logic device which combines a logic signal with a pulsed signal and outputs a set signal, a second logic device which logically combines the logic signal with a complementary pulsed signal and outputs a reset signal; and a latch device comprising storage means which hold a logic hold level to be tapped off as a stored logic state of the logic signal. The logic hold level is adjustable to a first logic level by a first push-pull transistor controlled by the set signal and to a second logic level by a second push-pull transistor controlled by the reset signal.

摘要翻译： 脉冲静态触发器包括将逻辑信号与脉冲信号组合并输出设定信号的第一逻辑器件，将逻辑信号与互补脉冲信号逻辑组合并输出复位信号的第二逻辑器件; 以及锁存装置，其包括存储装置，其保持要作为逻辑信号的存储的逻辑状态被分接的逻辑保持电平。 逻辑保持电平由被设置信号控制的第一推挽晶体调节到第一逻辑电平，并且由复位信号控制的第二推挽晶体调节到第二逻辑电平。

公开(公告)号：US07898836B2

公开(公告)日：2011-03-01

申请号：US12106927

申请日：2008-04-21

申请人： Thomas Kuenemund ,  Karl Zapf ,  Artur Wroblewski

发明人： Thomas Kuenemund ,  Karl Zapf ,  Artur Wroblewski

IPC分类号： G11C17/00

CPC分类号： G11C17/12 ,  G11C17/18

摘要： An array of masked memory cells including a first memory cell in a first column and a second memory cell in a second different column, wherein the first memory cell is capable of being accessed, so as to output, dependent on a first binary mask signal, a first binary value at a first output and a second binary value at a second output or vice versa, wherein the second memory cell is capable of being accessed, so as to output, dependent on a second binary mask signal, a first binary value at a third output and a second binary value at a fourth output or vice versa, and wherein the second and the third outputs of the memory cells are connected to an identical bit line of the memory array.

摘要翻译： 一种掩蔽存储单元的阵列，包括第一列中的第一存储单元和第二不同列中的第二存储单元，其中第一存储单元能够被访问，以便根据第一二进制掩码信号输出， 在第一输出处的第一二进制值和第二输出处的第二二进制值，反之亦然，其中第二存储器单元能够被访问，以便根据第二二进制掩码信号输出第二二进制值 第三输出和第二二进制值在第四输出或反之亦然，并且其中存储器单元的第二和第三输出连接到存储器阵列的相同位线。

公开(公告)号：US20090323389A1

公开(公告)日：2009-12-31

申请号：US12106927

申请日：2008-04-21

申请人： THOMAS KUENEMUND ,  Karl Zapf ,  Artur Wroblewski

发明人： THOMAS KUENEMUND ,  Karl Zapf ,  Artur Wroblewski

IPC分类号： G11C17/00 ,  G11C7/00

CPC分类号： G11C17/12 ,  G11C17/18

摘要： An array of masked memory cells including a first memory cell in a first column and a second memory cell in a second different column, wherein the first memory cell is capable of being accessed, so as to output, dependent on a first binary mask signal, a first binary value at a first output and a second binary value at a second output or vice versa, wherein the second memory cell is capable of being accessed, so as to output, dependent on a second binary mask signal, a first binary value at a third output and a second binary value at a fourth output or vice versa, and wherein the second and the third outputs of the memory cells are connected to an identical bit line of the memory array.

摘要翻译： 一种掩蔽存储单元的阵列，包括第一列中的第一存储单元和第二不同列中的第二存储单元，其中第一存储单元能够被访问，以便根据第一二进制掩码信号输出， 在第一输出处的第一二进制值和第二输出处的第二二进制值，反之亦然，其中第二存储器单元能够被访问，以便根据第二二进制掩码信号输出第二二进制值 第三输出和第二二进制值在第四输出或反之亦然，并且其中存储器单元的第二和第三输出连接到存储器阵列的相同位线。

公开(公告)号：US4271461A

公开(公告)日：1981-06-02

申请号：US36070

申请日：1979-05-04

申请人： Kurt Hoffmann ,  Karl Zapf

发明人： Kurt Hoffmann ,  Karl Zapf

IPC分类号： G11C11/407 ,  H02M3/07 ,  H02P13/22

CPC分类号： H02M3/07

摘要： A clock-controlled dc converter is provided in integrated semiconductor MOS technology and serves the supply voltage of integrated MOS circuits, particularly dynamic memories. The converter comprises a clock pulse generator having two outputs, supplying sequences of clock pulses which are inverted with respect to one another, which pulses are connected to the two clock pulse inputs of a first pulse level shifter. The first pulse level shifter comprises a bistable flip-flop lying at a supply potential, and which is switched as a level shifter. The two outputs of the first level shifter are connected, on the one hand, to the output of a voltage converter by way of the source-drain circuit of a respective field effect transistor. On the other hand, the two outputs are connected to the supply input of a respective pulse voltage doubler, which are in turn directly charged by a respective output of the clock pulse generator. The two pulse voltage doublers supply the clock pulse supply for a second pulse level shifter, likewise constructed as a bistable flip-flop, by way of the two outputs of which the connection between the outputs of the first level shifter and the output of the voltage comparator is controlled. The doubled supply voltage appears at the output of the voltage converter.

摘要翻译： 集成半导体MOS技术提供时钟控制的直流转换器，并为集成的MOS电路，特别是动态存储器提供电源电压。 该转换器包括具有两个输出的时钟脉冲发生器，提供相对于彼此反相的时钟脉冲序列，哪些脉冲连接到第一脉冲电平移位器的两个时钟脉冲输入。 第一脉冲电平移位器包括位于电源电位的双稳态触发器，并被切换为电平移位器。 一方面，第一电平移位器的两个输出端通过各自的场效应晶体管的源极 - 漏极电路连接到电压转换器的输出端。 另一方面，两个输出端连接到相应的脉冲倍压器的电源输入端，这些脉冲倍压器又由时钟脉冲发生器的相应输出端直接充电。 两个脉冲电压倍增器为同样构造为双稳态触发器的第二脉冲电平移位器提供时钟脉冲电源，通过其两个输出，第一电平移位器的输出与电压的输出之间的连接 比较器被控制。 在电压转换器的输出端出现双倍的电源电压。