公开(公告)号：US08188780B2

公开(公告)日：2012-05-29

申请号：US11648194

申请日：2006-12-29

申请人： Christian Pacha ,  Siegmar Köppe ,  Karl Zapf

发明人： Christian Pacha ,  Siegmar Köppe ,  Karl Zapf

IPC分类号： H03K3/00

CPC分类号： H03K3/35625 ,  H03K3/012

摘要： A pulsed static flip-flop comprises a first logic device which combines a logic signal with a pulsed signal and outputs a set signal, a second logic device which logically combines the logic signal with a complementary pulsed signal and outputs a reset signal; and a latch device comprising storage means which hold a logic hold level to be tapped off as a stored logic state of the logic signal. The logic hold level is adjustable to a first logic level by a first push-pull transistor controlled by the set signal and to a second logic level by a second push-pull transistor controlled by the reset signal.

摘要翻译： 脉冲静态触发器包括将逻辑信号与脉冲信号组合并输出设定信号的第一逻辑器件，将逻辑信号与互补脉冲信号逻辑组合并输出复位信号的第二逻辑器件; 以及锁存装置，其包括存储装置，其保持要作为逻辑信号的存储的逻辑状态被分接的逻辑保持电平。 逻辑保持电平由被设置信号控制的第一推挽晶体调节到第一逻辑电平，并且由复位信号控制的第二推挽晶体调节到第二逻辑电平。

公开(公告)号：US20070182473A1

公开(公告)日：2007-08-09

申请号：US11648194

申请日：2006-12-29

申请人： Christian Pacha ,  Siegmar Koppe ,  Karl Zapf

发明人： Christian Pacha ,  Siegmar Koppe ,  Karl Zapf

IPC分类号： H03K3/00

CPC分类号： H03K3/35625 ,  H03K3/012

摘要： A pulsed static flip-flop comprises a first logic device which combines a logic signal with a pulsed signal and outputs a set signal, a second logic device which logically combines the logic signal with a complementary pulsed signal and outputs a reset signal; and a latch device comprising storage means which hold a logic hold level to be tapped off as a stored logic state of the logic signal. The logic hold level is adjustable to a first logic level by a first push-pull transistor controlled by the set signal and to a second logic level by a second push-pull transistor controlled by the reset signal.

摘要翻译： 脉冲静态触发器包括将逻辑信号与脉冲信号组合并输出设定信号的第一逻辑器件，将逻辑信号与互补脉冲信号逻辑组合并输出复位信号的第二逻辑器件; 以及锁存装置，其包括存储装置，其保持要作为逻辑信号的存储的逻辑状态被分接的逻辑保持电平。 逻辑保持电平由被设置信号控制的第一推挽晶体调节到第一逻辑电平，并且由复位信号控制的第二推挽晶体调节到第二逻辑电平。

公开(公告)号：US08338251B2

公开(公告)日：2012-12-25

申请号：US13472514

申请日：2012-05-16

申请人： Joerg Berthold ,  Christian Pacha ,  Klaus von Arnim

发明人： Joerg Berthold ,  Christian Pacha ,  Klaus von Arnim

IPC分类号： H01L21/336

CPC分类号： G11C11/412 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/04 ,  H01L29/785

摘要： One or more embodiments of the invention relate to a method comprising: treating a fin of a first n-channel access transistor in a static random access memory cell to have a lower charge carrier mobility than a fin of a first n-channel pull-down transistor in a first inverter in the memory cell, the first n-channel access transistor being coupled between a first bit line and a first node of the first inverter; and treating a fin of a second n-channel access transistor in the memory cell to have a lower charge carrier mobility than a fin of a second n-channel pull-down transistor in a second inverter in the memory cell, the second n-channel access transistor being coupled between a second bit line and a second node of the second inverter.

摘要翻译： 本发明的一个或多个实施例涉及一种方法，包括：处理静态随机存取存储器单元中的第一n沟道存取晶体管的鳍以具有比第一n沟道下拉的鳍更低的载流子迁移率 晶体管在存储单元中的第一反相器中，第一n沟道存取晶体管耦合在第一反相器的第一位线和第一节点之间; 以及处理所述存储单元中的第二n沟道存取晶体管的鳍以具有比所述存储单元中的第二反相器中的第二n沟道下拉晶体管的鳍更低的电荷载流子迁移率，所述第二n沟道 存取晶体管耦合在第二反相器的第二位线和第二节点之间。

公开(公告)号：US08310027B2

公开(公告)日：2012-11-13

申请号：US12138319

申请日：2008-06-12

申请人： Christian Russ ,  Christian Pacha ,  Snezana Jenei ,  Klaus Schruefer

发明人： Christian Russ ,  Christian Pacha ,  Snezana Jenei ,  Klaus Schruefer

IPC分类号： H01L29/73

CPC分类号： H01L29/7317 ,  H01L21/8228 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/082 ,  H01L27/092 ,  H01L29/66265 ,  H01L29/74 ,  H01L29/785

摘要： Embodiments relate to a bipolar transistor that includes a body region having a fin structure. At least one terminal region may be formed over at least a portion of the body region. The at least one terminal region may be formed as an epitaxially grown region. Embodiments also relate to a vertically integrated electronic device that includes a first terminal region, a second terminal region and a third terminal region. The second terminal region may be arranged over at least a portion of the third terminal region, and at least two of the first, second and third terminal regions may be formed as epitaxially grown regions.

摘要翻译： 实施例涉及一种双极晶体管，其包括具有翅片结构的主体区域。 可以在身体区域的至少一部分上形成至少一个末端区域。 至少一个末端区域可以形成为外延生长区域。 实施例还涉及一种垂直集成的电子设备，其包括第一端子区域，第二端子区域和第三端子区域。 第二端子区域可以布置在第三端子区域的至少一部分上，并且第一，第二和第三端子区域中的至少两个可以形成为外延生长区域。

公开(公告)号：US20120268184A1

公开(公告)日：2012-10-25

申请号：US13535422

申请日：2012-06-28

申请人： Thomas Baumann ,  Christian Pacha ,  Stephan Henzler ,  Peter Huber

发明人： Thomas Baumann ,  Christian Pacha ,  Stephan Henzler ,  Peter Huber

IPC分类号： H03H11/26

CPC分类号： H03L7/0814 ,  H03K5/135 ,  H03K2005/00058

摘要： The present disclosure relates to on-chip self calibrating delay monitoring circuitry.

摘要翻译： 本公开涉及片上自校准延迟监测电路。

公开(公告)号：US20120026781A1

公开(公告)日：2012-02-02

申请号：US13270592

申请日：2011-10-11

申请人： Christian Pacha ,  Tim Schönauer ,  Michael Kund

发明人： Christian Pacha ,  Tim Schönauer ,  Michael Kund

IPC分类号： G11C11/00

CPC分类号： G11C13/0011 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/32 ,  H01L27/2436 ,  H01L29/785 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1273 ,  H01L45/145

摘要： A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.

摘要翻译： 存储器件包括具有接触区域的翅片的多栅极场效应晶体管（MuGFET）。 可编程存储元件邻接鳍片接触区域。

公开(公告)号：US20110095347A1

公开(公告)日：2011-04-28

申请号：US12986875

申请日：2011-01-07

申请人： Christian Russ ,  Christian Pacha ,  Snezana Jenei ,  Klaus Schruefer

发明人： Christian Russ ,  Christian Pacha ,  Snezana Jenei ,  Klaus Schruefer

IPC分类号： H01L29/78 ,  H01L21/36

CPC分类号： H01L29/861 ,  H01L29/6609 ,  H01L29/66356 ,  H01L29/7391

摘要： Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.

摘要翻译： 一些实施例涉及在半导体本体和设置在半导体本体的掺杂区域上的外延膜之间出现垂直二极管活性的装置。 一些实施例包括引起垂直和横向二极管活动的装置。 一些实施例包括用于翅片半导体装置的门控垂直二极管。 工艺实施例包括形成垂直二极管装置。

公开(公告)号：US20110013668A1

公开(公告)日：2011-01-20

申请号：US12888528

申请日：2010-09-23

申请人： Christian Pacha ,  Thomas Schulz ,  Klaus Von Arnim

发明人： Christian Pacha ,  Thomas Schulz ,  Klaus Von Arnim

IPC分类号： G01K7/01 ,  H01L29/74 ,  H01L27/06

CPC分类号： G01K7/015 ,  H01L27/0727 ,  H01L27/1203 ,  H01L29/78606 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor circuit arrangement and a method for temperature detection is disclosed. One embodiment includes a semiconductor substrate, on which is formed a first insulating layer and thereon a thin active semiconductor region, which is laterally delimited by a second insulating layer. In the active semiconductor region, a first and second doping zone are formed on the surface of the first insulating layer for the definition of a channel zone, wherein there is formed at the surface of the channel zone a gate dielectric and thereon a control electrode for the realization of a field effect transistor. In the active semiconductor region, a diode doping zone is formed on the surface of the first insulating layer, which zone realizes a measuring diode via a diode side area with the first or second doping zone and is delimited by the second insulating layer at its further side areas.

摘要翻译： 公开了半导体电路装置和温度检测方法。 一个实施例包括半导体衬底，其上形成有由第二绝缘层横向界定的第一绝缘层和其上的薄的有源半导体区域。 在有源半导体区域中，在第一绝缘层的表面上形成第一和第二掺杂区，用于定义沟道区，其中在沟道区的表面形成栅极电介质，并且在其上形成控制电极 实现场效应晶体管。 在有源半导体区域中，在第一绝缘层的表面上形成二极管掺杂区，该区通过具有第一或第二掺杂区的二极管侧区实现测量二极管，并且在其另外的第二绝缘层处限定第二绝缘层 边区。

公开(公告)号：US07820505B2

公开(公告)日：2010-10-26

申请号：US11862640

申请日：2007-09-27

申请人： Ralf Brederlow ,  Jessica Hartwich ,  Christian Pacha ,  Wolfgang Rösner ,  Thomas Schulz

发明人： Ralf Brederlow ,  Jessica Hartwich ,  Christian Pacha ,  Wolfgang Rösner ,  Thomas Schulz

IPC分类号： H01L21/8242

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/1211 ,  H01L27/13 ,  H01L28/60 ,  H01L29/66795

摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.

摘要翻译： 集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。 电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。 近电极区域是单晶体并且包含多个网状物。 或者，存在FET，其中沟道区域是有源区域，FET包含具有相对的控制电极的幅材，该栅极通过由沟道区域与厚绝缘区域隔离的连接区域连接。 厚的绝缘区域比控制电极绝缘区域厚。 控制电极含有与远电极区域相同的材料。

公开(公告)号：US07733157B2

公开(公告)日：2010-06-08

申请号：US10583538

申请日：2004-12-03

申请人： Ralf Brederlow ,  Jeongwook Koh ,  Christian Pacha ,  Roland Thewes

发明人： Ralf Brederlow ,  Jeongwook Koh ,  Christian Pacha ,  Roland Thewes

IPC分类号： H03K17/687

CPC分类号： H03K17/162 ,  H01L2924/0002 ,  H01L2924/00

摘要： Noise-reducing transistor arrangement having first and second field effect transistors (FETs) having source terminals coupled together, drain terminals coupled together, and control terminals for application of a first or second signal. A clock generator unit is configured to provide the first and second signals alternately to the FETs with an alternating frequency which is at least as great as the cut-off frequency of the noise characteristic of the FETs, or with a reciprocal alternating frequency which is less than a mean lifetime of an occupation state of a defect in the boundary region between channel region and gate insulating layer of the FETs. The first signal is applied to the control terminal of the first FET and, simultaneously, the second signal to the control terminal of the second FET. The second signal is applied to the control terminal of the first FET and, simultaneously, the first signal to the control terminal of the second FET.

摘要翻译： 具有第一和第二场效应晶体管（FET）的降噪晶体管装置，其具有耦合在一起的源极端子，耦合在一起的漏极端子和用于施加第一或第二信号的控制端子。 时钟发生器单元被配置为以至少与FET的噪声特性的截止频率一样大的交变频率或者具有较小的互逆交变频率来向FET施加交替的第一和第二信号 比FET的沟道区域和栅极绝缘层之间的边界区域的缺陷的占用状态的平均寿命长。 第一信号被施加到第一FET的控制端子，并且同时将第二信号施加到第二FET的控制端子。 第二信号被施加到第一FET的控制端，同时将第一信号施加到第二FET的控制端。