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1.发明申请公开(公告)号：US20100011253A1
公开(公告)日：2010-01-14
申请号：US12308240
申请日：2007-09-26
申请人： Christian Wenzel-Benner , Markus Bartel , Thomas Kahnert , Peter Sautter , Carsten Gebauer , Harald Tschentscher , Berthold Fehrenbacher , Achim Schaefer , Gotthilf Koerner , Andreas Frey , Helmut Binder , Bernd Stoehr
发明人： Christian Wenzel-Benner , Markus Bartel , Thomas Kahnert , Peter Sautter , Carsten Gebauer , Harald Tschentscher , Berthold Fehrenbacher , Achim Schaefer , Gotthilf Koerner , Andreas Frey , Helmut Binder , Bernd Stoehr
CPC分类号： H04L25/45 , H04J3/047 , H04L2001/0096
摘要： A circuit arrangement, having a circuit and a computer unit is provided, in which the circuit and the computer unit are connected to one another via multiple lines for transmitting a number of signals which are embodied as information signals. The circuit has a multiplexer for combining signals, the multiplexer being connected to the computer unit via an additional line.
摘要翻译： 提供具有电路和计算机单元的电路装置，其中电路和计算机单元经由多条线相互连接，用于发送体现为信息信号的多个信号。 电路具有用于组合信号的多路复用器，多路复用器经由附加线路连接到计算机单元。
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2.发明申请Circuit Arrangement for a Data Processing System and Method for Data Processing 有权数据处理系统的电路布置和数据处理方法公开(公告)号：US20130111189A1
公开(公告)日：2013-05-02
申请号：US13638125
申请日：2011-03-18
申请人： Eberhard Boehl , Ruben Bartholomae , Matthias Knauss , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Dieter Thoss , Bernhard Mader , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Rolf Kurrer , Bernd Becker , Bernard Pawlok
发明人： Eberhard Boehl , Ruben Bartholomae , Matthias Knauss , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Dieter Thoss , Bernhard Mader , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Rolf Kurrer , Bernd Becker , Bernard Pawlok
IPC分类号： G06F15/76
摘要： A circuit arrangement for a data processing system is configured to process data in multiple modules. The circuit arrangement is configured to provide a clock as well as a time base and/or a base of at least one further physical quantity for each of the multiple modules. The circuit arrangement also comprises a central routing unit, which is connected to several of the multiple modules. Via the central routing unit, the modules can periodically exchange data based on the time base and/or on the base of the at least one further physical quantity. The several modules are configured to process data independently of and in parallel to other modules of the several modules.
摘要翻译： 用于数据处理系统的电路装置被配置为处理多个模块中的数据。 电路布置被配置为为多个模块中的每一个提供时钟以及时基和/或至少一个另外的物理量的基极。 电路装置还包括中央路由单元，其连接到多个模块中的若干个。 通过中央路由单元，模块可以基于时基和/或基于至少一个其他物理量周期性地交换数据。 多个模块被配置为独立于和并行地处理数个模块的其他模块的数据。
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公开(公告)号：US20130227331A1
公开(公告)日：2013-08-29
申请号：US13637061
申请日：2011-03-16
申请人： Eberhard Boehl , Ruben Bartholomae , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Axel Aue , Dieter Thoss , Thomas Lindenkreuz , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Bernd Becker
发明人： Eberhard Boehl , Ruben Bartholomae , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Axel Aue , Dieter Thoss , Thomas Lindenkreuz , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Bernd Becker
IPC分类号： G06F1/10
摘要： A circuit arrangement for a data processing system is configured to process data in a plurality of modules. The circuit arrangement is configured such that each module is provided with at least one clock pulse, a time base and a base of at least one additional physical variable. The circuit arrangement also comprises a central routing unit to which the plurality of modules are coupled and via which the plurality of modules can periodically exchange data amongst themselves, based on the time base and/or the base of other physical variables. Each module is configured independently and parallel to other modules of the plurality of modules in order to process data. The circuit arrangement is employed in a corresponding method.
摘要翻译： 用于数据处理系统的电路装置被配置为处理多个模块中的数据。 电路布置被配置为使得每个模块被提供有至少一个时钟脉冲，时基和至少一个附加物理变量的基极。 电路装置还包括中央路由单元，多个模块耦合到该中央路由单元，多个模块可以经由该中央路由单元基于时基和/或其他物理变量的基础周期性地在它们之间交换数据。 每个模块独立配置并且与多个模块中的其他模块并行配置，以便处理数据。 电路装置采用相应的方法。
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4.发明授权Circuit arrangement for a data processing system and method for data processing 有权数据处理系统的电路布置和数据处理方法公开(公告)号：US09367516B2
公开(公告)日：2016-06-14
申请号：US13638125
申请日：2011-03-18
申请人： Eberhard Boehl , Ruben Bartholomae , Matthias Knauss , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Dieter Thoss , Bernhard Mader , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Rolf Kurrer , Bernd Becker , Bernard Pawlok
发明人： Eberhard Boehl , Ruben Bartholomae , Matthias Knauss , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Dieter Thoss , Bernhard Mader , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Rolf Kurrer , Bernd Becker , Bernard Pawlok
摘要： A circuit arrangement for a data processing system is configured to process data in multiple modules. The circuit arrangement is configured to provide a clock as well as a time base and/or a base of at least one further physical quantity for each of the multiple modules. The circuit arrangement also comprises a central routing unit, which is connected to several of the multiple modules. Via the central routing unit, the modules can periodically exchange data based on the time base and/or on the base of the at least one further physical quantity. The several modules are configured to process data independently of and in parallel to other modules of the several modules.
摘要翻译： 用于数据处理系统的电路装置被配置为处理多个模块中的数据。 电路布置被配置为为多个模块中的每一个提供时钟以及时基和/或至少一个另外的物理量的基极。 电路装置还包括中央路由单元，其连接到多个模块中的若干个。 通过中央路由单元，模块可以基于时基和/或基于至少一个其他物理量周期性地交换数据。 多个模块被配置为独立于和并行地处理数个模块的其他模块的数据。
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公开(公告)号：US09342096B2
公开(公告)日：2016-05-17
申请号：US13637061
申请日：2011-03-16
申请人： Eberhard Boehl , Ruben Bartholomae , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Axel Aue , Dieter Thoss , Thomas Lindenkreuz , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Bernd Becker
发明人： Eberhard Boehl , Ruben Bartholomae , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Axel Aue , Dieter Thoss , Thomas Lindenkreuz , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Bernd Becker
摘要： A circuit arrangement for a data processing system is configured to process data in a plurality of modules. The circuit arrangement is configured such that each module is provided with at least one clock pulse, a time base and a base of at least one additional physical variable. The circuit arrangement also comprises a central routing unit to which the plurality of modules are coupled and via which the plurality of modules can periodically exchange data amongst themselves, based on the time base and/or the base of other physical variables. Each module is configured independently and parallel to other modules of the plurality of modules in order to process data. The circuit arrangement is employed in a corresponding method.
摘要翻译： 用于数据处理系统的电路装置被配置为处理多个模块中的数据。 电路布置被配置为使得每个模块被提供有至少一个时钟脉冲，时基和至少一个附加物理变量的基极。 电路装置还包括中央路由单元，多个模块耦合到该中央路由单元，多个模块可以经由该中央路由单元基于时基和/或其他物理变量的基础周期性地在它们之间交换数据。 每个模块独立配置并且与多个模块中的其他模块并行配置，以便处理数据。 电路装置采用相应的方法。
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