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    Multi-chip module with a high-rate interface
    1.
    发明授权
    Multi-chip module with a high-rate interface 有权

    公开(公告)号：US09843538B2

    公开(公告)日：2017-12-12

    申请号：US14599411

    申请日：2015-01-16

    申请人： BROADCOM CORPORATION

    发明人： William Calvin Woodruff

    IPC分类号： H04L12/935 ,  H04J3/04 ,  H04J3/06 ,  H04L12/741 ,  H04L12/931

    CPC分类号： H04L49/30 ,  H04J3/047 ,  H04J3/0697 ,  H04L45/745 ,  H04L49/40

    摘要： A multi-chip module (MCM) may include a substrate, and first and second physical-layer (PHY) chips mounted on the substrate. In some implementations, the first PHY chip includes a multiplexer and a PHY circuit. The multiplexer is configured to receive a multiplexed data stream from a media access control (MAC) device, to demultiplex the multiplexed data stream into first and second data streams, to output the first data stream to the PHY circuit, and to output the second data stream to the second PHY chip. In some implementations, the first PHY includes a router and a PHY circuit. The router is configured to receive a plurality of data packets from a MAC device, to route one or more of the data packets having a first address to the PHY circuit, and to route one or more of the data packets having a second address to the second PHY chip.

    HIGH SPEED SERIALIZER USING QUADRATURE CLOCKS
    2.
    发明申请
    HIGH SPEED SERIALIZER USING QUADRATURE CLOCKS 审中-公开

    公开(公告)号：US20170310412A1

    公开(公告)日：2017-10-26

    申请号：US15137187

    申请日：2016-04-25

    申请人： APPLIED MICRO CIRCUITS CORPORATION

    发明人： Vijay Gupta ,  Tarun Gupta

    IPC分类号： H04J3/06 ,  H04L7/00

    CPC分类号： H04J3/0691 ,  H03M9/00 ,  H04J3/047 ,  H04J3/0682 ,  H04J3/0685 ,  H04L7/0037

    摘要： Techniques efficiently serialize multiple data streams using quadrature clocks. Serializer employs first, second, third, and fourth clock signals. Serializer receives multiple data streams via registers, with each of four paths comprising a register, buffer, and switch, with registers of first and fourth paths associated with third clock signal, and registers of second and third paths associated with first clock signal, and with switches of first and fourth paths associated with first clock signal, and switches of second and third paths associated with third clock signal. Switches of first and second paths transfer respective data bits to fifth switch via another buffer, wherein fifth switch is associated with a delayed second clock signal of a time delay component (TDC). Switches of third and fourth paths transfer respective data bits to sixth switch via another buffer, wherein sixth switch is associated with a delayed fourth clock signal of TDC.

    Transceiver unit
    5.
    发明授权
    Transceiver unit 有权
    收发单元

    公开(公告)号：US09584137B2

    公开(公告)日：2017-02-28

    申请号：US13300728

    申请日：2011-11-21

    申请人： Kenneth Hann

    发明人： Kenneth Hann

    IPC分类号： H04B10/00 ,  H03L7/07 ,  H04J3/04

    CPC分类号： H03L7/07 ,  H04J3/047

    摘要： A phase synchronized optical master-slave loop comprises at the slave-end a processor (105) configured to include a first timing signal into a bit stream to be transmitted to the master-end, detect a second timing signal from a bit stream received from the master-end, and calculate a phase difference between a regenerated phase signal and a reference phase signal on the basis of a transmission moment of the first timing signal, a first time-stamp indicating a reception moment of the first timing signal at the master-end, a reception moment of the second timing signal, and a second time-stamp indicating a transmission moment of the second timing signal from the master-end. The processor is configured to read the time stamps from the received bit stream that corresponds to a received light signal according to a reception line-code. Thus, conversion of data format is not necessary for the phase synchronization.

    摘要翻译： 相位同步光学主从环包括在从端处的处理器（105），被配置为将第一定时信号包括在要发送到主端的比特流中，从从第一定时信号接收的比特流中检测第二定时信号 并且基于第一定时信号的传输力矩计算再生相位信号和参考相位信号之间的相位差，第一时间戳表示主机上的第一定时信号的接收力矩 -end，第二定时信号的接收时刻，以及指示来自主端的第二定时信号的发送时刻的第二时间戳。 处理器被配置为根据接收线路码从接收到的比特流读取对应于接收到的光信号的时间戳。 因此，数据格式的转换对于相位同步是不必要的。

    Data transmission method and device
    7.
    发明授权
    Data transmission method and device 有权
    数据传输方法及装置

    公开(公告)号：US09520971B2

    公开(公告)日：2016-12-13

    申请号：US14415619

    申请日：2012-07-17

    申请人： Peng Hao ,  Lining Yang ,  Can Huang ,  Zhen Gao

    发明人： Peng Hao ,  Lining Yang ,  Can Huang ,  Zhen Gao

    IPC分类号： H04W4/00 ,  H04L5/00 ,  H04J3/04 ,  H04J3/16

    CPC分类号： H04L5/0044 ,  H04J3/047 ,  H04J3/1605

    摘要： Provided is a data transmission method and device. The method includes: receiving IQ data from an uplink; according to the mapping of the IQ data in a Common Public Radio Interface (CPRI) basic frame, utilizing at least one storage unit to sequence the IQ data; combining a control word with the sequenced IQ data to form CPRI data, and transmitting the CPRI data. The solution utilizes at least one storage unit to sequence the IQ data, and extracts the sequenced data for a CPRI framing operation. This solution is simple in hardware processing and low in realization complexity. The change and upgrade of the transmission bandwidth of multiple modes (single mode or mixed mode) during system upgrade only occur on software layer without affecting the realization of hardware, thus having good flexibility.

    摘要翻译： 提供了一种数据传输方法和装置。 该方法包括：从上行链路接收IQ数据; 根据公共无线电接口（CPRI）基本帧中的IQ数据的映射，利用至少一个存储单元对IQ数据进行排序; 将控制字与排序的IQ数据组合以形成CPRI数据，并发送CPRI数据。 该解决方案利用至少一个存储单元对IQ数据进行排序，并提取CPRI成帧操作的排序数据。 该解决方案在硬件处理上很简单，实现复杂度低。 系统升级过程中多种模式（单模或混合模式）的传输带宽的变化和升级只发生在软件层，而不影响硬件的实现，具有良好的灵活性。

    SIGNAL MULTIPLEXER
    8.
    发明申请
    SIGNAL MULTIPLEXER 审中-公开
    信号多路复用器

    公开(公告)号：US20160308522A1

    公开(公告)日：2016-10-20

    申请号：US15103387

    申请日：2014-11-14

    申请人： THINE ELECTRONICS, INC.

    发明人： Yusuke FUJITA ,  Satoshi MIURA ,  Shunichi KUBO

    IPC分类号： H03K17/16 ,  H03K17/693

    CPC分类号： H03K17/162 ,  H03K17/693 ,  H03K19/00 ,  H03K19/1733 ,  H03K19/1737 ,  H04J3/047

    摘要： The signal multiplexer 1 inputs two selection signals CLK , CLK that sequentially reach significant levels, inputs two input signals IN , IN , and outputs, from an output terminal 14, a signal OUT that depends on an m-th input signal IN of the two input signals when an m-th selection signal CLK of the two selection signals is at the significant level. The signal multiplexer 1 includes a resistance unit 20 and two drive units 301, 302. Each of the drive units 30m includes a driving switch 31m, a selecting switch 32m, and a potential stabilizing switch 33m. When one of the selecting switch 32m and the potential stabilizing switch 33m in each of the drive units 30m is in a closed state, the other is in an open state.

    摘要翻译： 信号复用器1输入顺序达到显着电平的两个选择信号CLK 1，CLK <2，输入两个输入信号IN 1，IN <2>，并从输出端14输出信号OUT 当两个选择信号的第m选择信号CLK 处于高电平时，取决于两个输入信号的第m个输入信号IN