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公开(公告)号：US08258925B2
公开(公告)日：2012-09-04
申请号：US12057644
申请日：2008-03-28
IPC分类号： H04Q5/22
摘要： A frequency synthesizer for providing clock signals with different frequencies for corresponding band transceivers and associated frequency synthesizing method are provided. The frequency synthesizer includes a phase-locked loop module having a single voltage controlled oscillator, a first frequency divider and a second frequency divider. At first, the single voltage controlled oscillator is activated to generate a primary clock signal. The first frequency divider frequency-divides the primary clock signal to generate a first clock signal for a first band transceiver. The first clock signal is further frequency-divided into a second clock signal for a second band transceiver. Therefore, the frequency synthesizer with the single voltage controlled oscillator can generate clock signals covering more than one frequency band.
摘要翻译： 提供了一种频率合成器，用于为相应的频带收发机提供不同频率的时钟信号和相关的频率合成方法。 频率合成器包括具有单个压控振荡器的锁相环模块，第一分频器和第二分频器。 首先，单个压控振荡器被激活以产生主时钟信号。 第一分频器对主时钟信号进行分频，以产生用于第一频带收发器的第一时钟信号。 第一时钟信号被进一步分频为第二频带收发器的第二时钟信号。 因此，具有单个压控振荡器的频率合成器可以产生覆盖多于一个频带的时钟信号。
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2.发明申请CLOCK GENERATOR, METHOD FOR GENERATING CLOCK SIGNAL AND FRACTIONAL PHASE LOCK LOOP THEREOF 有权时钟发生器，用于产生时钟信号的方法及其相位锁相环公开(公告)号：US20080238498A1
公开(公告)日：2008-10-02
申请号：US12046527
申请日：2008-03-12
摘要： A clock generator includes a delta sigma modulator, a counter and a first phase lock loop. The delta sigma modulator sequentially generates a plurality of variable parameters according to a predetermined value and a first input clock signal. The counter, which is connected to the delta sigma modulator, is used to generate an output clock signal in accordance with a counting value and a second input clock signal. The counting value is relevant to the variable parameters. The first phase lock loop, which is connected to the output of the counter, is used to generate an objective clock signal in accordance with the output clock signal.
摘要翻译： 时钟发生器包括ΔΣ调制器，计数器和第一锁相环。 ΔΣ调制器根据预定值和第一输入时钟信号顺序产生多个可变参数。 连接到Δ-Σ调制器的计数器用于根据计数值和第二输入时钟信号产生输出时钟信号。 计数值与变量参数相关。 连接到计数器的输出的第一锁相环用于根据输出时钟信号产生目标时钟信号。
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3.发明授权Clock generator, method for generating clock signal and fractional phase lock loop thereof 有权时钟发生器，用于产生时钟信号的方法和其分数锁相环公开(公告)号：US07944265B2
公开(公告)日：2011-05-17
申请号：US12046527
申请日：2008-03-12
摘要： A clock generator includes a delta sigma modulator, a counter and a first phase lock loop. The delta sigma modulator sequentially generates a plurality of variable parameters according to a predetermined value and a first input clock signal. The counter, which is connected to the delta sigma modulator, is used to generate an output clock signal in accordance with a counting value and a second input clock signal. The counting value is relevant to the variable parameters. The first phase lock loop, which is connected to the output of the counter, is used to generate an objective clock signal in accordance with the output clock signal.
摘要翻译： 时钟发生器包括ΔΣ调制器，计数器和第一锁相环。 ΔΣ调制器根据预定值和第一输入时钟信号顺序产生多个可变参数。 连接到Δ-Σ调制器的计数器用于根据计数值和第二输入时钟信号产生输出时钟信号。 计数值与变量参数相关。 连接到计数器的输出的第一锁相环用于根据输出时钟信号产生目标时钟信号。
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