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1.发明申请公开(公告)号：US20120011482A1
公开(公告)日：2012-01-12
申请号：US12832180
申请日：2010-07-08
申请人： Chuck ALPERT , Zhuo Li , Arjen Alexander Mets , Ying Zhou
发明人： Chuck ALPERT , Zhuo Li , Arjen Alexander Mets , Ying Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/08
摘要： A method, system, and computer usable program product for multiple threshold voltage cell families (mVt families) based integrated circuit design are provided in the illustrative embodiments. The integrated circuit includes cells, and a cell includes an electronic component. A design process is initialized by using cells from the mVt families in the design. The cells from the mVt families are included in iterative manipulation of the design. The cells from the mVt families are further included in violation cleanup and subsequent steps of the design process. A version of the design is produced that is usable to implement the circuit with the cells from the mVt families.
摘要翻译： 在说明性实施例中提供了用于多个阈值电压单元族（mVt系列）的集成电路设计的方法，系统和计算机可用程序产品。 集成电路包括单元，单元包括电子元件。 通过使用设计中的mVt系列的单元格初始化设计过程。 来自mVt系列的单元格被包含在设计的迭代操作中。 来自mVt系列的单元格进一步包含在违规清理和设计过程的后续步骤中。 产生了一种可用于使用来自mVt系列的单元实现电路的设计版本。
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公开(公告)号：US08656334B2
公开(公告)日：2014-02-18
申请号：US12832180
申请日：2010-07-08
申请人： Charles Jay Alpert , Zhuo Li , Arjen Alexander Mets , Ying Zhou
发明人： Charles Jay Alpert , Zhuo Li , Arjen Alexander Mets , Ying Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/08
摘要： A method, system, and computer usable program product for multiple threshold voltage cell families (mVt families) based integrated circuit design are provided in the illustrative embodiments. The integrated circuit includes cells, and a cell includes an electronic component. A design process is initialized by using cells from the mVt families in the design. The cells from the mVt families are included in iterative manipulation of the design. The cells from the mVt families are further included in violation cleanup and subsequent steps of the design process. A version of the design is produced that is usable to implement the circuit with the cells from the mVt families.
摘要翻译： 在说明性实施例中提供了用于多个阈值电压单元族（mVt系列）的集成电路设计的方法，系统和计算机可用程序产品。 集成电路包括单元，单元包括电子元件。 通过使用设计中的mVt系列的单元格初始化设计过程。 来自mVt系列的单元格被包含在设计的迭代操作中。 来自mVt系列的单元格进一步包含在违规清理和设计过程的后续步骤中。 产生了一种可用于使用来自mVt系列的单元实现电路的设计版本。
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公开(公告)号：US08370782B2
公开(公告)日：2013-02-05
申请号：US12823232
申请日：2010-06-25
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method, system, and computer usable program product for buffer-aware routing in integrated circuit design are provided in the illustrative embodiments. The design has cells, and the circuit includes buffers and wires. A route is received from a set of routes. The route couples a first point in the circuit to a second point in the circuit and including at least one buffer between the first point and the second point. A determination is made whether the route violates a set of hard constraints for a part of the circuit, where the set of hard constraints includes a reach length constraint. In response to the route not violating any hard constraint in the set of hard constraints, the route is selected as a buffer-aware routing solution between the first and the second points in the circuit.
摘要翻译： 在说明性实施例中提供了用于集成电路设计中用于缓冲器感知路由的方法，系统和计算机可用程序产品。 该设计有电池，电路包括缓冲器和电线。 从一组路由接收到路由。 路线将电路中的第一点耦合到电路中的第二点，并且包括在第一点和第二点之间的至少一个缓冲器。 确定路线是否违反了电路的一部分的一组硬约束，其中硬约束集合包括到达长度约束。 响应于路由不违反硬约束集合中的任何硬约束，路由被选择为电路中的第一和第二点之间的缓冲器感知路由解决方案。
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公开(公告)号：US20110320992A1
公开(公告)日：2011-12-29
申请号：US12823232
申请日：2010-06-25
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method, system, and computer usable program product for buffer-aware routing in integrated circuit design are provided in the illustrative embodiments. The design has cells, and the circuit includes buffers and wires. A route is received from a set of routes. The route couples a first point in the circuit to a second point in the circuit and including at least one buffer between the first point and the second point. A determination is made whether the route violates a set of hard constraints for a part of the circuit, where the set of hard constraints includes a reach length constraint. In response to the route not violating any hard constraint in the set of hard constraints, the route is selected as a buffer-aware routing solution between the first and the second points in the circuit.
摘要翻译： 在说明性实施例中提供了用于集成电路设计中用于缓冲器感知路由的方法，系统和计算机可用程序产品。 该设计有电池，电路包括缓冲器和电线。 从一组路由接收到路由。 路线将电路中的第一点耦合到电路中的第二点，并且包括在第一点和第二点之间的至少一个缓冲器。 确定路线是否违反了电路的一部分的一组硬约束，其中硬约束集合包括到达长度约束。 响应于路由不违反硬约束集合中的任何硬约束，路由被选择为电路中的第一和第二点之间的缓冲器感知路由解决方案。
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公开(公告)号：US08539400B2
公开(公告)日：2013-09-17
申请号：US13248119
申请日：2011-09-29
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Mechanisms are provided for generating a logic design of an integrated circuit device. An initial logic design representation of the integrated circuit device is received and one or more areas of the initial logic design representation are identified where logic elements in the one or more areas can be replaced with one or more multiplexer tree structures. Logic elements in the one or more areas of the initial logic design representation are replaced with multiplexer tree structures to generate a modified logic design representation. The modified logic design representation is output to a physical synthesis system to generate a physical layout of the integrated circuit device based on the modified logic design representation.
摘要翻译： 提供用于产生集成电路器件的逻辑设计的机构。 接收集成电路设备的初始逻辑设计表示，并且识别初始逻辑设计表示的一个或多个区域，其中一个或多个区域中的逻辑元件可被一个或多个多路复用器树结构替代。 初始逻辑设计表示的一个或多个区域中的逻辑元件被多路复用器树结构替代以生成修改的逻辑设计表示。 经修改的逻辑设计表示被输出到物理合成系统，以基于经修改的逻辑设计表示来生成集成电路器件的物理布局。
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公开(公告)号：US20120284683A1
公开(公告)日：2012-11-08
申请号：US13102776
申请日：2011-05-06
申请人： Charles Jay Alpert , Zhuo Li , Stephen Thomas Quay , Ying Zhou
发明人： Charles Jay Alpert , Zhuo Li , Stephen Thomas Quay , Ying Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5077 , G06F2217/84
摘要： A method, system, and computer program product for timing driven routing in a design of an integrated circuit (IC) are provided in the illustrative embodiments. A router application executing in a data processing system performs a pre-global routing optimization of the design. A plurality of wirelength target constraints are set on a plurality of subsets of a set of nets in the design. Global routing is performed on the design. The design is adjusted using wires placed in the design during the global routing. A priority is assigned to each net in the set of nets. Detailed routing is performed on the design.
摘要翻译： 在说明性实施例中提供了用于在集成电路（IC）的设计中的定时驱动路由的方法，系统和计算机程序产品。 在数据处理系统中执行的路由器应用程序执行设计的全局前路由优化。 在设计中的一组网络的多个子集上设置多个线长目标约束。 在设计上执行全局路由。 在全局路由期间，使用设计中的电线来调整设计。 优先级分配给网络集合中的每个网络。 在设计上执行详细的路由。
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公开(公告)号：US20100223586A1
公开(公告)日：2010-09-02
申请号：US12395373
申请日：2009-02-27
申请人： Zhuo Li , Charles J. Alpert , Damir Jamsek , Chin Ngai Sze , Ying Zhou
发明人： Zhuo Li , Charles J. Alpert , Damir Jamsek , Chin Ngai Sze , Ying Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The present disclosure is directed to a method for determining a plurality of buffer insertion locations in a net for an integrated circuit design. The method may comprise calculating a plurality of resistive-capacitive (RC) influences in parallel, each RC influence corresponding to one of a plurality of buffering options available for a first sub-tree for the addition of a wire segment to the first sub-tree; updating the plurality of RC influences for the addition of a buffer for the first sub-tree, the buffer comprising one of a plurality of buffer types; and merging the first sub-tree with a second sub-tree in parallel by grouping the plurality of buffering options available for the first sub-tree and a plurality of buffering options available for the second sub-tree into a plurality of merging groups, and merging at least two groups of the plurality of merging groups in parallel.
摘要翻译： 本公开涉及一种用于确定用于集成电路设计的网络中的多个缓冲器插入位置的方法。 该方法可以包括并行计算多个电阻 - 电容（RC）影响，每个RC影响对应于可用于第一子树的多个缓冲选项之一，用于将线段添加到第一子树 ; 更新所述多个RC影响以添加所述第一子树的缓冲器，所述缓冲器包括多个缓冲器类型之一; 以及通过将可用于所述第一子树的所述多个缓冲选项和可用于所述第二子树的多个缓冲选项分组成多个合并组来并行地将所述第一子树与第二子树合并，以及 合并至少两组多个合并组。
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公开(公告)号：US08386985B2
公开(公告)日：2013-02-26
申请号：US13102776
申请日：2011-05-06
申请人： Charles Jay Alpert , Zhuo Li , Stephen Thomas Quay , Ying Zhou
发明人： Charles Jay Alpert , Zhuo Li , Stephen Thomas Quay , Ying Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5077 , G06F2217/84
摘要： A method, system, and computer program product for timing driven routing in a design of an integrated circuit (IC) are provided in the illustrative embodiments. A router application executing in a data processing system performs a pre-global routing optimization of the design. A plurality of wirelength target constraints are set on a plurality of subsets of a set of nets in the design. Global routing is performed on the design. The design is adjusted using wires placed in the design during the global routing. A priority is assigned to each net in the set of nets. Detailed routing is performed on the design.
摘要翻译： 在说明性实施例中提供了用于在集成电路（IC）的设计中的定时驱动路由的方法，系统和计算机程序产品。 在数据处理系统中执行的路由器应用程序执行设计的全局前路由优化。 在设计中的一组网络的多个子集上设置多个线长目标约束。 在设计上执行全局路由。 在全局路由期间，使用设计中的电线来调整设计。 优先级分配给网络集合中的每个网络。 在设计上执行详细的路由。
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公开(公告)号：US08037438B2
公开(公告)日：2011-10-11
申请号：US12395373
申请日：2009-02-27
申请人： Zhuo Li , Charles J. Alpert , Damir Jamsek , Chin Ngai Sze , Ying Zhou
发明人： Zhuo Li , Charles J. Alpert , Damir Jamsek , Chin Ngai Sze , Ying Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The present disclosure is directed to a method for determining a plurality of buffer insertion locations in a net for an integrated circuit design. The method may comprise calculating a plurality of resistive-capacitive (RC) influences in parallel, each RC influence corresponding to one of a plurality of buffering options available for a first sub-tree for the addition of a wire segment to the first sub-tree; updating the plurality of RC influences for the addition of a buffer for the first sub-tree, the buffer comprising one of a plurality of buffer types; and merging the first sub-tree with a second sub-tree in parallel by grouping the plurality of buffering options available for the first sub-tree and a plurality of buffering options available for the second sub-tree into a plurality of merging groups, and merging at least two groups of the plurality of merging groups in parallel.
摘要翻译： 本公开涉及一种用于确定用于集成电路设计的网络中的多个缓冲器插入位置的方法。 该方法可以包括并行计算多个电阻 - 电容（RC）影响，每个RC影响对应于可用于第一子树的多个缓冲选项之一，用于将线段添加到第一子树 ; 更新所述多个RC影响以添加所述第一子树的缓冲器，所述缓冲器包括多个缓冲器类型之一; 以及通过将可用于所述第一子树的所述多个缓冲选项和可用于所述第二子树的多个缓冲选项分组成多个合并组来并行地将所述第一子树与第二子树合并，以及 合并至少两组多个合并组。
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公开(公告)号：US08677305B2
公开(公告)日：2014-03-18
申请号：US13488065
申请日：2012-06-04
申请人： Charles Jay Alpert , Joseph Nicolas Kozhaya , Zhuo Li , Joseph J Palumbo , Haifeng Qian , Phillip John Restle , Chin Ngai Sze , Ying Zhou
发明人： Charles Jay Alpert , Joseph Nicolas Kozhaya , Zhuo Li , Joseph J Palumbo , Haifeng Qian , Phillip John Restle , Chin Ngai Sze , Ying Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/62
摘要： An electronic automation design tool with a sink locator unit creates clusters of loads from a plurality of loads within a sector of a clock network design based on balancing magnitudes of the loads among the clusters of loads and based on minimal delays of each of the clusters and respective ones of a plurality of sink locations in the sector of the clock network design. The tool determines centers of the clusters of loads, and sink locations corresponding to the centers of the clusters for connecting output terminal points of sector buffers are determined. Each of the sector buffers drive a clock signal to a corresponding one of the clusters of loads.
摘要翻译： 具有接收器定位器单元的电子自动化设计工具基于平衡负载集群中的负载的大小并且基于每个集群的最小延迟，从时钟网络设计的扇区内的多个负载中产生负载集群，以及 在时钟网络设计的扇区中的多个接收器位置中的相应的一个。 该工具确定负载集群的中心，并确定与簇的中心对应的接收位置，以连接扇区缓冲器的输出端点。 每个扇区缓冲器将时钟信号驱动到相应的一组负载。
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