公开(公告)号：US07696557B2

公开(公告)日：2010-04-13

申请号：US11706587

申请日：2007-02-15

申请人： Chun Chen ,  Andrei Mihnea ,  Kirk Prall

发明人： Chun Chen ,  Andrei Mihnea ,  Kirk Prall

IPC分类号： H01L29/788

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11521

摘要： Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

摘要翻译： 在隔离阱中形成的浮栅场效应晶体管或存储单元在制造非易失性存储器阵列和器件中是有用的。 这种浮栅存储器单元的列与包含列中的每个存储器单元的源极/漏极区的阱相关联。 这些阱与阵列的其他列的源/漏区隔离。 可以使用Fowler-Nordheim隧道来编程和擦除这种浮动栅极存储器单元，无论是单独的还是以块或块为基础的。

公开(公告)号：US20070164348A1

公开(公告)日：2007-07-19

申请号：US11706587

申请日：2007-02-15

申请人： Chun Chen ,  Andrei Mihnea ,  Kirk Prall

发明人： Chun Chen ,  Andrei Mihnea ,  Kirk Prall

IPC分类号： H01L29/788

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11521

摘要： Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

摘要翻译： 在隔离阱中形成的浮栅场效应晶体管或存储单元在制造非易失性存储器阵列和器件中是有用的。 这种浮栅存储器单元的列与包含列中的每个存储器单元的源极/漏极区的阱相关联。 这些阱与阵列的其他列的源/漏区隔离。 可以使用Fowler-Nordheim隧道来编程和擦除这种浮动栅极存储器单元，无论是单独的还是以块或块为基础的。

公开(公告)号：US07199422B2

公开(公告)日：2007-04-03

申请号：US11006177

申请日：2004-12-06

申请人： Chun Chen ,  Andrei Mihnea ,  Kirk Prall

发明人： Chun Chen ,  Andrei Mihnea ,  Kirk Prall

IPC分类号： H01L29/788

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11521

摘要： Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

摘要翻译： 在隔离阱中形成的浮栅场效应晶体管或存储单元在制造非易失性存储器阵列和器件中是有用的。 这种浮栅存储器单元的列与包含列中的每个存储器单元的源极/漏极区的阱相关联。 这些阱与阵列的其他列的源/漏区隔离。 可以使用Fowler-Nordheim隧道来编程和擦除这种浮动栅极存储器单元，无论是单独的还是以块或块为基础的。

公开(公告)号：US20050099846A1

公开(公告)日：2005-05-12

申请号：US11006177

申请日：2004-12-06

申请人： Chun Chen ,  Andrei Mihnea ,  Kirk Prall

发明人： Chun Chen ,  Andrei Mihnea ,  Kirk Prall

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11521

摘要： Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

摘要翻译： 在隔离阱中形成的浮栅场效应晶体管或存储单元在制造非易失性存储器阵列和器件中是有用的。 这种浮栅存储器单元的列与包含列中的每个存储器单元的源极/漏极区的阱相关联。 这些阱与阵列的其他列的源/漏区隔离。 可以使用Fowler-Nordheim隧道来编程和擦除这种浮动栅极存储器单元，无论是单独的还是以块或块为基础的。

公开(公告)号：US06984547B2

公开(公告)日：2006-01-10

申请号：US10662074

申请日：2003-09-12

申请人： Chun Chen ,  Andrei Mihnea ,  Kirk Prall

发明人： Chun Chen ,  Andrei Mihnea ,  Kirk Prall

IPC分类号： H01L21/82

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11521

摘要： Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

摘要翻译： 在隔离阱中形成的浮栅场效应晶体管或存储单元在制造非易失性存储器阵列和器件中是有用的。 这种浮栅存储器单元的列与包含列中的每个存储器单元的源/漏区的阱相关联。 这些阱与阵列的其他列的源/漏区隔离。 可以使用Fowler-Nordheim隧道来编程和擦除这种浮动栅极存储器单元，无论是单独的还是以块或块为基础的。

公开(公告)号：US06649453B1

公开(公告)日：2003-11-18

申请号：US10230597

申请日：2002-08-29

申请人： Chun Chen ,  Andrei Mihnea ,  Kirk Prall

发明人： Chun Chen ,  Andrei Mihnea ,  Kirk Prall

IPC分类号： H01L2182

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11521

摘要： Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

摘要翻译： 在隔离阱中形成的浮栅场效应晶体管或存储单元在制造非易失性存储器阵列和器件中是有用的。 这种浮栅存储器单元的列与包含列中的每个存储器单元的源极/漏极区的阱相关联。 这些阱与阵列的其他列的源/漏区隔离。 可以使用Fowler-Nordheim隧道来编程和擦除这种浮动栅极存储器单元，无论是单独的还是以块或块为基础的。

公开(公告)号：US06930350B2

公开(公告)日：2005-08-16

申请号：US10655251

申请日：2003-09-04

申请人： Chun Chen ,  Andrei Mihnea ,  Kirk Prall

发明人： Chun Chen ,  Andrei Mihnea ,  Kirk Prall

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11521

摘要： Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

摘要翻译： 在隔离阱中形成的浮栅场效应晶体管或存储单元在制造非易失性存储器阵列和器件中是有用的。 这种浮栅存储器单元的列与包含列中的每个存储器单元的源极/漏极区的阱相关联。 这些阱与阵列的其他列的源/漏区隔离。 可以使用Fowler-Nordheim隧道来编程和擦除这种浮动栅极存储器单元，无论是单独的还是以块或块为基础的。

公开(公告)号：US20060067128A1

公开(公告)日：2006-03-30

申请号：US11217920

申请日：2005-09-01

申请人： Andrei Mihnea ,  Chun Chen

发明人： Andrei Mihnea ,  Chun Chen

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C16/08 ,  G11C16/14 ,  H01L27/115

摘要： Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

公开(公告)号：US20060007747A1

公开(公告)日：2006-01-12

申请号：US11217820

申请日：2005-09-01

申请人： Andrei Mihnea ,  Chun Chen

发明人： Andrei Mihnea ,  Chun Chen

IPC分类号： G11C11/34

CPC分类号： G11C16/16 ,  G11C16/08 ,  G11C16/14 ,  H01L27/115

摘要： Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

公开(公告)号：US06563741B2

公开(公告)日：2003-05-13

申请号：US09772667

申请日：2001-01-30

申请人： Andrei Mihnea ,  Chun Chen ,  Paul Rudeck ,  Andrew R. Bicksler

发明人： Andrei Mihnea ,  Chun Chen ,  Paul Rudeck ,  Andrew R. Bicksler

IPC分类号： G11C1604

CPC分类号： G11C16/3409 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3404

摘要： A non-volatile memory device includes an improved method for erasing a block of stack-gate single transistor flash memory cells. The memory performs an efficient and controllable mode of programming, referred to as block convergence. During an erase operation, one or more electrical erase pulses of fixed number, duration and voltage waveform are applied to memory cells in an addressable block of the memory device array. The erase pulse(s) fully erase all bits in the block. A block convergence operation is applied simultaneously to all cells in the block. The block convergence operation brings a threshold voltage of cells, which may have become over-erased during the erase operation, to a controlled level. A reverse-bias pulse, capable of inducing band-to-band tunnelling across one junction in the structure of the flash memory cells, is applied to a first junction. The other junction receives either a reverse bias or floating potential. The memory can implement several biasing schemes while performing the block convergence operation.