公开(公告)号：US20090085858A1

公开(公告)日：2009-04-02

申请号：US11927697

申请日：2007-10-30

申请人： Chun-Yuan Hsu ,  Chih-Jen Shih ,  Che-Cheng Kuo ,  Cheng-Hung Tsai ,  I-Cheng Shih

发明人： Chun-Yuan Hsu ,  Chih-Jen Shih ,  Che-Cheng Kuo ,  Cheng-Hung Tsai ,  I-Cheng Shih

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/0297 ,  G09G2320/0209 ,  G09G2320/0242

摘要： A driving circuit applied to a display panel includes a driving unit for generating a plurality of driving signals to drive a plurality of pixels in the display panel, and a plurality of multiplexers coupled to the driving unit and the plurality of pixels. Each multiplexer of the plurality of multiplexers is utilized for sequentially transmitting a plurality of driving signals to a plurality of sub-pixels of a corresponding pixel, where two adjacent pixels utilize different driving sequences of the sub-pixels to drive their sub-pixels.

摘要翻译： 应用于显示面板的驱动电路包括用于产生多个驱动信号以驱动显示面板中的多个像素的驱动单元和耦合到驱动单元和多个像素的多个多路复用器。 多个多路复用器的每个多路复用器用于将多个驱动信号顺序地发送到相应像素的多个子像素，其中两个相邻像素利用子像素的不同驱动序列来驱动它们的子像素。

公开(公告)号：US07764761B2

公开(公告)日：2010-07-27

申请号：US12187384

申请日：2008-08-07

申请人： Chih-Jen Shih ,  Chun-Yuan Hsu ,  Che-Cheng Kuo ,  Chun-Kuo Yu

发明人： Chih-Jen Shih ,  Chun-Yuan Hsu ,  Che-Cheng Kuo ,  Chun-Kuo Yu

IPC分类号： G11C19/00

CPC分类号： H03K19/00315 ,  G09G3/3677 ,  G09G2310/0286 ,  G11C19/28

摘要： A shift register apparatus and a method thereof are provided. The technique manner submitted by the present invention utilizes two NMOS transistors for pulling down the voltage level of the scan signals output by the shift registers within the shift register apparatus to the low level gate voltage, wherein one of the NMOS transistors is controlled by a control unit, and the other NMOS transistor is controlled by a clock signal or the inverted clock signal provided to the shift registers. Therefore, shifting amount of the threshold voltage of those NMOS transistors can trend to be flat, and the reliability of those NMOS transistors can be promoted. In addition, since only one control unit is needed to dispose in each shift register so that the layout area of whole shift register apparatus can be reduced, and the panel with narrow frame size also can be achieved by the present invention.

摘要翻译： 提供一种移位寄存装置及其方法。 本发明提供的技术方法利用两个NMOS晶体管来将由移位寄存器装置内的移位寄存器输出的扫描信号的电压电平降低到低电平门电压，其中一个NMOS晶体管由一个控制 单元，另一个NMOS晶体管由提供给移位寄存器的时钟信号或反相时钟信号控制。 因此，那些NMOS晶体管的阈值电压的移动量趋向于平坦，并且可以促进那些NMOS晶体管的可靠性。 此外，由于只需要一个控制单元来配置在每个移位寄存器中，从而可以减少整个移位寄存器装置的布局区域，并且通过本发明也可以实现具有窄帧大小的面板。

公开(公告)号：US20100002827A1

公开(公告)日：2010-01-07

申请号：US12187384

申请日：2008-08-07

申请人： Chih-Jen Shih ,  Chun-Yuan Hsu ,  Che-Cheng Kuo ,  Chun-Kuo Yu

发明人： Chih-Jen Shih ,  Chun-Yuan Hsu ,  Che-Cheng Kuo ,  Chun-Kuo Yu

IPC分类号： H03K23/46

CPC分类号： H03K19/00315 ,  G09G3/3677 ,  G09G2310/0286 ,  G11C19/28

摘要： A shift register apparatus and a method thereof are provided. The technique manner submitted by the present invention utilizes two NMOS transistors for pulling down the voltage level of the scan signals output by the shift registers within the shift register apparatus to the low level gate voltage, wherein one of the NMOS transistors is controlled by a control unit, and the other NMOS transistor is controlled by a clock signal or the inverted clock signal provided to the shift registers. Therefore, shifting amount of the threshold voltage of those NMOS transistors can trend to be flat, and the reliability of those NMOS transistors can be promoted. In addition, since only one control unit is needed to dispose in each shift register so that the layout area of whole shift register apparatus can be reduced, and the panel with narrow frame size also can be achieved by the present invention.

摘要翻译： 提供一种移位寄存装置及其方法。 本发明提供的技术方法利用两个NMOS晶体管来将由移位寄存器装置内的移位寄存器输出的扫描信号的电压电平降低到低电平门电压，其中一个NMOS晶体管由一个控制 单元，另一个NMOS晶体管由提供给移位寄存器的时钟信号或反相时钟信号控制。 因此，那些NMOS晶体管的阈值电压的移动量趋向于平坦，并且可以促进那些NMOS晶体管的可靠性。 此外，由于只需要一个控制单元来配置在每个移位寄存器中，从而可以减少整个移位寄存器装置的布局区域，并且通过本发明也可以实现具有窄帧大小的面板。

公开(公告)号：US20080106504A1

公开(公告)日：2008-05-08

申请号：US11754309

申请日：2007-05-27

申请人： Hsiang-Yun Wei ,  Chun-Yuan Hsu ,  Che-Cheng Kuo ,  Chun-Yao Huang ,  Jan-Ruei Lin

发明人： Hsiang-Yun Wei ,  Chun-Yuan Hsu ,  Che-Cheng Kuo ,  Chun-Yao Huang ,  Jan-Ruei Lin

IPC分类号： G09G3/32

CPC分类号： G09G3/3233 ,  G09G2320/0233

摘要： The present invention discloses an OLED driving device, including a first switch transistor, a first transistor, a second switch transistor, a storage capacitor and a second transistor. The first switch transistor is used to receive a data signal, and output the data signal by the control of a first scan signal. The first transistor is used to compensate the effect of the threshold voltage of the second transistor. The second switch transistor is used to receive a voltage signal, and output the voltage signal by the control of a second scan signal. The storage capacitor is used to store a data voltage. The second transistor is electrically connected to the second switch transistor through the storage capacitor. The present invention can efficiently release the charges from the storage capacitor, enhance display effect, and change the input voltage level for adapting different operating voltages of integrate circuits.

摘要翻译： 本发明公开了一种OLED驱动装置，包括第一开关晶体管，第一晶体管，第二开关晶体管，存储电容器和第二晶体管。 第一开关晶体管用于接收数据信号，并通过第一扫描信号的控制来输出数据信号。 第一晶体管用于补偿第二晶体管的阈值电压的影响。 第二开关晶体管用于接收电压信号，并且通过控制第二扫描信号来输出电压信号。 存储电容用于存储数据电压。 第二晶体管通过存储电容器电连接到第二开关晶体管。 本发明可以有效地从存储电容器中释放电荷，增强显示效果，并且改变输入电压电平以适应集成电路的不同工作电压。

公开(公告)号：US07777705B2

公开(公告)日：2010-08-17

申请号：US11754309

申请日：2007-05-27

申请人： Hsiang-Yun Wei ,  Chun-Yuan Hsu ,  Che-Cheng Kuo ,  Chun-Yao Huang ,  Jan-Ruei Lin

发明人： Hsiang-Yun Wei ,  Chun-Yuan Hsu ,  Che-Cheng Kuo ,  Chun-Yao Huang ,  Jan-Ruei Lin

IPC分类号： G09G3/32

CPC分类号： G09G3/3233 ,  G09G2320/0233

摘要： The present invention discloses an OLED driving device, including a first switch transistor, a first transistor, a second switch transistor, a storage capacitor and a second transistor. The first switch transistor is used to receive a data signal, and output the data signal by the control of a first scan signal. The first transistor is used to compensate the effect of the threshold voltage of the second transistor. The second switch transistor is used to receive a voltage signal, and output the voltage signal by the control of a second scan signal. The storage capacitor is used to store a data voltage. The second transistor is electrically connected to the second switch transistor through the storage capacitor. The present invention can efficiently release the charges from the storage capacitor, enhance display effect, and change the input voltage level for adapting different operating voltages of integrate circuits.

摘要翻译： 本发明公开了一种OLED驱动装置，包括第一开关晶体管，第一晶体管，第二开关晶体管，存储电容器和第二晶体管。 第一开关晶体管用于接收数据信号，并通过第一扫描信号的控制来输出数据信号。 第一晶体管用于补偿第二晶体管的阈值电压的影响。 第二开关晶体管用于接收电压信号，并且通过控制第二扫描信号来输出电压信号。 存储电容用于存储数据电压。 第二晶体管通过存储电容器电连接到第二开关晶体管。 本发明可以有效地从存储电容器中释放电荷，增强显示效果，并且改变输入电压电平以适应集成电路的不同工作电压。

公开(公告)号：US07447292B2

公开(公告)日：2008-11-04

申请号：US11772833

申请日：2007-07-03

申请人： Chun-Yuan Hsu ,  Jan-Ruei Lin ,  Hsiang-Yun Wei ,  Che-Cheng Kuo ,  Chun-Yao Huang

发明人： Chun-Yuan Hsu ,  Jan-Ruei Lin ,  Hsiang-Yun Wei ,  Che-Cheng Kuo ,  Chun-Yao Huang

IPC分类号： G11C19/00

CPC分类号： G11C19/28

摘要： A shift register, a driving circuit and a display device using the same are disclosed. The shift register includes a 1st and a 2nd rectifying elements and 1st˜4th transistors. 1st source/drains of the 1st˜3rd transistors receive a common voltage respectively. The gates of the 1st and 3rd transistors and a 2nd source/drain of the 2nd transistor are coupled to a 2nd terminal of the 2nd rectifying element. The gates of the 2nd and 4th transistors and a 2nd source/drain of the 1st transistor are coupled to a 2nd terminal of the 1st rectifying element. A 1st source/drain of the 4th transistor is coupled to a 2nd source/drain of the 3rd transistor. The 1st terminals of the 1st and 2nd rectifying elements respectively receive input signals and a 1st clock signal. A 2nd source/drain of the 4th transistor receives a 2nd clock signal.

摘要翻译： 公开了一种移位寄存器，驱动电路和使用该移位寄存器的显示装置。 移位寄存器包括一个第一和第二个整流元件和一个第一至第四个第三晶体管。 1 〜3 晶体管的1 / SUP源极/漏极分别接收公共电压。 第一晶体管和第三晶体管的栅极和第二晶体管的第二和/或第二源极/漏极 耦合到第2和/或（SUP）整流元件的第2端子。 第二晶体管的第二和第四和第四晶体管的栅极和第一晶体管的第二和/或第二源极/漏极 耦合到第1级校正元件的2端子端子。 第四晶体管的源极/漏极的第一个源极/漏极耦合到第三晶体管的第二源极/漏极， SUP>晶体管。 第一和第二和/或第二整流元件的第一端子分别接收输入信号和第一时钟 信号。 第4 晶体管的源极/漏极的第2个源极/漏极接收第2个时钟信号。

公开(公告)号：US20080130822A1

公开(公告)日：2008-06-05

申请号：US11772833

申请日：2007-07-03

申请人： Chun-Yuan Hsu ,  Jan-Ruei Lin ,  Hsiang-Yun Wei ,  Che-Cheng Kuo ,  Chun-Yao Huang

发明人： Chun-Yuan Hsu ,  Jan-Ruei Lin ,  Hsiang-Yun Wei ,  Che-Cheng Kuo ,  Chun-Yao Huang

IPC分类号： G11C19/28

CPC分类号： G11C19/28

摘要： A shift register, a driving circuit and a display device using the same are disclosed. The shift register includes a 1st and a 2nd rectifying elements and 1st˜4th transistors. 1st source/drains of the 1st˜3rd transistors receive a common voltage respectively. The gates of the 1st and 3rd transistors and a 2nd source/drain of the 2nd transistor are coupled to a 2nd terminal of the 2nd rectifying element. The gates of the 2nd and 4th transistors and a 2nd source/drain of the 1st transistor are coupled to a 2nd terminal of the 1st rectifying element. A 1st source/drain of the 4th transistor is coupled to a 2nd source/drain of the 3rd transistor. The 1st terminals of the 1st and 2nd rectifying elements respectively receive input signals and a 1st clock signal. A 2nd source/drain of the 4th transistor receives a 2nd clock signal.

摘要翻译： 公开了一种移位寄存器，驱动电路和使用该移位寄存器的显示装置。 移位寄存器包括一个第一和第二个整流元件和一个第一至第四个第三晶体管。 1 〜3 晶体管的1 / SUP源极/漏极分别接收公共电压。 第一晶体管和第三晶体管的栅极和第二晶体管的第二和/或第二源极/漏极 耦合到第2和/或（SUP）整流元件的第2端子。 第二晶体管的第二和第四和第四晶体管的栅极和第一晶体管的第二和/或第二源极/漏极 耦合到第1级校正元件的2端子端子。 第四晶体管的源极/漏极的第一个源极/漏极耦合到第三晶体管的第二源极/漏极， SUP>晶体管。 第一和第二和/或第二整流元件的第一端子分别接收输入信号和第一时钟 信号。 第4个晶体管的源极/漏极的第2个/第2个源极/漏极接收第二个时钟信号。

公开(公告)号：US08269712B2

公开(公告)日：2012-09-18

申请号：US12465630

申请日：2009-05-13

申请人： Chih-Jen Shih ,  Chun-Kuo Yu ,  Chun-Yuan Hsu

发明人： Chih-Jen Shih ,  Chun-Kuo Yu ,  Chun-Yuan Hsu

IPC分类号： G09G3/36 ,  H03K19/096

CPC分类号： G11C19/28 ,  G09G3/3677

摘要： A high-reliability gate driving circuit is disclosed for providing a plurality of gate signals to plural gate lines respectively. The gate driving circuit includes a plurality of shift register stages. Each shift register stage includes a pull-up unit, an energy-store unit, a buffer unit, a discharging unit, a first pull-down unit, a second pull-down unit and a control unit. The pull-up unit pulls up a gate signal according to a driving control voltage and a first clock. The buffer unit receives an input signal. The energy-store unit provides the driving control voltage through performing a charging process based on the input signal. The first pull-down unit pulls down the gate signal according to a control signal. The second pull-down unit pulls down the gate signal according to a second clock having a phase opposite to the first clock. The control unit generates the control signal based on the gate signal.

摘要翻译： 公开了一种高可靠性栅极驱动电路，用于分别向多个栅极线提供多个栅极信号。 栅极驱动电路包括多个移位寄存器级。 每个移位寄存器级包括上拉单元，能量存储单元，缓冲单元，放电单元，第一下拉单元，第二下拉单元和控制单元。 上拉单元根据驱动控制电压和第一个时钟上拉一个门信号。 缓冲单元接收输入信号。 能量存储单元通过基于输入信号进行充电处理来提供驱动控制电压。 第一个下拉单元根据控制信号拉下门信号。 第二下拉单元根据具有与第一时钟相反的相位的第二时钟来拉低门信号。 控制单元根据门信号产生控制信号。

公开(公告)号：US20100177068A1

公开(公告)日：2010-07-15

申请号：US12465630

申请日：2009-05-13

申请人： Chih-Jen Shih ,  Chun-Kuo Yu ,  Chun-Yuan Hsu

发明人： Chih-Jen Shih ,  Chun-Kuo Yu ,  Chun-Yuan Hsu

IPC分类号： G06F3/038 ,  G09G3/36

CPC分类号： G11C19/28 ,  G09G3/3677

摘要： A high-reliability gate driving circuit is disclosed for providing a plurality of gate signals to plural gate lines respectively. The gate driving circuit includes a plurality of shift register stages. Each shift register stage includes a pull-up unit, an energy-store unit, a buffer unit, a discharging unit, a first pull-down unit, a second pull-down unit and a control unit. The pull-up unit pulls up a gate signal according to a driving control voltage and a first clock. The buffer unit receives an input signal. The energy-store unit provides the driving control voltage through performing a charging process based on the input signal. The first pull-down unit pulls down the gate signal according to a control signal. The second pull-down unit pulls down the gate signal according to a second clock having a phase opposite to the first clock. The control unit generates the control signal based on the gate signal.

摘要翻译： 公开了一种高可靠性栅极驱动电路，用于分别向多个栅极线提供多个栅极信号。 栅极驱动电路包括多个移位寄存器级。 每个移位寄存器级包括上拉单元，能量存储单元，缓冲单元，放电单元，第一下拉单元，第二下拉单元和控制单元。 上拉单元根据驱动控制电压和第一个时钟上拉一个门信号。 缓冲单元接收输入信号。 能量存储单元通过基于输入信号进行充电处理来提供驱动控制电压。 第一个下拉单元根据控制信号拉下门信号。 第二下拉单元根据具有与第一时钟相反的相位的第二时钟来拉低门信号。 控制单元根据门信号产生控制信号。

公开(公告)号：US08233583B2

公开(公告)日：2012-07-31

申请号：US12264244

申请日：2008-11-03

申请人： Cheng-Hung Tsai ,  Yi-Feng Liao ,  Chun-Yuan Hsu

发明人： Cheng-Hung Tsai ,  Yi-Feng Liao ,  Chun-Yuan Hsu

IPC分类号： G11C19/00

CPC分类号： G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/28

摘要： A shift register and a display driver thereof are provided. The display driver submitted by the present invention can be directly disposed on a glass substrate of a liquid crystal display (LCD) panel to replace a scan driver commonly used in prior art, so that the cost of the liquid crystal display can be reduced. In addition, the stress taken by the output stage transistor of each shift register stage within the display driver submitted by the present invention can be reduced. Thus, each shift register stage has the highest reliability, and may consequently avoid the erroneous actions when each shift register stage is operated for a long time.

摘要翻译： 提供了移位寄存器及其显示驱动器。 通过本发明提供的显示驱动器可以直接设置在液晶显示器（LCD）面板的玻璃基板上，以代替现有技术中常用的扫描驱动器，从而可以降低液晶显示器的成本。 此外，可以减少由本发明提交的显示驱动器内的每个移位寄存器级的输出级晶体管所采取的应力。 因此，每个移位寄存器级具有最高的可靠性，并且因此可以避免每个移位寄存器级被长时间操作时的错误动作。