公开(公告)号：US20090085858A1

公开(公告)日：2009-04-02

申请号：US11927697

申请日：2007-10-30

申请人： Chun-Yuan Hsu ,  Chih-Jen Shih ,  Che-Cheng Kuo ,  Cheng-Hung Tsai ,  I-Cheng Shih

发明人： Chun-Yuan Hsu ,  Chih-Jen Shih ,  Che-Cheng Kuo ,  Cheng-Hung Tsai ,  I-Cheng Shih

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/0297 ,  G09G2320/0209 ,  G09G2320/0242

摘要： A driving circuit applied to a display panel includes a driving unit for generating a plurality of driving signals to drive a plurality of pixels in the display panel, and a plurality of multiplexers coupled to the driving unit and the plurality of pixels. Each multiplexer of the plurality of multiplexers is utilized for sequentially transmitting a plurality of driving signals to a plurality of sub-pixels of a corresponding pixel, where two adjacent pixels utilize different driving sequences of the sub-pixels to drive their sub-pixels.

摘要翻译： 应用于显示面板的驱动电路包括用于产生多个驱动信号以驱动显示面板中的多个像素的驱动单元和耦合到驱动单元和多个像素的多个多路复用器。 多个多路复用器的每个多路复用器用于将多个驱动信号顺序地发送到相应像素的多个子像素，其中两个相邻像素利用子像素的不同驱动序列来驱动它们的子像素。

公开(公告)号：US07764761B2

公开(公告)日：2010-07-27

申请号：US12187384

申请日：2008-08-07

申请人： Chih-Jen Shih ,  Chun-Yuan Hsu ,  Che-Cheng Kuo ,  Chun-Kuo Yu

发明人： Chih-Jen Shih ,  Chun-Yuan Hsu ,  Che-Cheng Kuo ,  Chun-Kuo Yu

IPC分类号： G11C19/00

CPC分类号： H03K19/00315 ,  G09G3/3677 ,  G09G2310/0286 ,  G11C19/28

摘要： A shift register apparatus and a method thereof are provided. The technique manner submitted by the present invention utilizes two NMOS transistors for pulling down the voltage level of the scan signals output by the shift registers within the shift register apparatus to the low level gate voltage, wherein one of the NMOS transistors is controlled by a control unit, and the other NMOS transistor is controlled by a clock signal or the inverted clock signal provided to the shift registers. Therefore, shifting amount of the threshold voltage of those NMOS transistors can trend to be flat, and the reliability of those NMOS transistors can be promoted. In addition, since only one control unit is needed to dispose in each shift register so that the layout area of whole shift register apparatus can be reduced, and the panel with narrow frame size also can be achieved by the present invention.

摘要翻译： 提供一种移位寄存装置及其方法。 本发明提供的技术方法利用两个NMOS晶体管来将由移位寄存器装置内的移位寄存器输出的扫描信号的电压电平降低到低电平门电压，其中一个NMOS晶体管由一个控制 单元，另一个NMOS晶体管由提供给移位寄存器的时钟信号或反相时钟信号控制。 因此，那些NMOS晶体管的阈值电压的移动量趋向于平坦，并且可以促进那些NMOS晶体管的可靠性。 此外，由于只需要一个控制单元来配置在每个移位寄存器中，从而可以减少整个移位寄存器装置的布局区域，并且通过本发明也可以实现具有窄帧大小的面板。

公开(公告)号：US20100002827A1

公开(公告)日：2010-01-07

申请号：US12187384

申请日：2008-08-07

申请人： Chih-Jen Shih ,  Chun-Yuan Hsu ,  Che-Cheng Kuo ,  Chun-Kuo Yu

发明人： Chih-Jen Shih ,  Chun-Yuan Hsu ,  Che-Cheng Kuo ,  Chun-Kuo Yu

IPC分类号： H03K23/46

CPC分类号： H03K19/00315 ,  G09G3/3677 ,  G09G2310/0286 ,  G11C19/28

摘要： A shift register apparatus and a method thereof are provided. The technique manner submitted by the present invention utilizes two NMOS transistors for pulling down the voltage level of the scan signals output by the shift registers within the shift register apparatus to the low level gate voltage, wherein one of the NMOS transistors is controlled by a control unit, and the other NMOS transistor is controlled by a clock signal or the inverted clock signal provided to the shift registers. Therefore, shifting amount of the threshold voltage of those NMOS transistors can trend to be flat, and the reliability of those NMOS transistors can be promoted. In addition, since only one control unit is needed to dispose in each shift register so that the layout area of whole shift register apparatus can be reduced, and the panel with narrow frame size also can be achieved by the present invention.

摘要翻译： 提供一种移位寄存装置及其方法。 本发明提供的技术方法利用两个NMOS晶体管来将由移位寄存器装置内的移位寄存器输出的扫描信号的电压电平降低到低电平门电压，其中一个NMOS晶体管由一个控制 单元，另一个NMOS晶体管由提供给移位寄存器的时钟信号或反相时钟信号控制。 因此，那些NMOS晶体管的阈值电压的移动量趋向于平坦，并且可以促进那些NMOS晶体管的可靠性。 此外，由于只需要一个控制单元来配置在每个移位寄存器中，从而可以减少整个移位寄存器装置的布局区域，并且通过本发明也可以实现具有窄帧大小的面板。

公开(公告)号：US08269712B2

公开(公告)日：2012-09-18

申请号：US12465630

申请日：2009-05-13

申请人： Chih-Jen Shih ,  Chun-Kuo Yu ,  Chun-Yuan Hsu

发明人： Chih-Jen Shih ,  Chun-Kuo Yu ,  Chun-Yuan Hsu

IPC分类号： G09G3/36 ,  H03K19/096

CPC分类号： G11C19/28 ,  G09G3/3677

摘要： A high-reliability gate driving circuit is disclosed for providing a plurality of gate signals to plural gate lines respectively. The gate driving circuit includes a plurality of shift register stages. Each shift register stage includes a pull-up unit, an energy-store unit, a buffer unit, a discharging unit, a first pull-down unit, a second pull-down unit and a control unit. The pull-up unit pulls up a gate signal according to a driving control voltage and a first clock. The buffer unit receives an input signal. The energy-store unit provides the driving control voltage through performing a charging process based on the input signal. The first pull-down unit pulls down the gate signal according to a control signal. The second pull-down unit pulls down the gate signal according to a second clock having a phase opposite to the first clock. The control unit generates the control signal based on the gate signal.

摘要翻译： 公开了一种高可靠性栅极驱动电路，用于分别向多个栅极线提供多个栅极信号。 栅极驱动电路包括多个移位寄存器级。 每个移位寄存器级包括上拉单元，能量存储单元，缓冲单元，放电单元，第一下拉单元，第二下拉单元和控制单元。 上拉单元根据驱动控制电压和第一个时钟上拉一个门信号。 缓冲单元接收输入信号。 能量存储单元通过基于输入信号进行充电处理来提供驱动控制电压。 第一个下拉单元根据控制信号拉下门信号。 第二下拉单元根据具有与第一时钟相反的相位的第二时钟来拉低门信号。 控制单元根据门信号产生控制信号。

公开(公告)号：US20100177068A1

公开(公告)日：2010-07-15

申请号：US12465630

申请日：2009-05-13

申请人： Chih-Jen Shih ,  Chun-Kuo Yu ,  Chun-Yuan Hsu

发明人： Chih-Jen Shih ,  Chun-Kuo Yu ,  Chun-Yuan Hsu

IPC分类号： G06F3/038 ,  G09G3/36

CPC分类号： G11C19/28 ,  G09G3/3677

摘要： A high-reliability gate driving circuit is disclosed for providing a plurality of gate signals to plural gate lines respectively. The gate driving circuit includes a plurality of shift register stages. Each shift register stage includes a pull-up unit, an energy-store unit, a buffer unit, a discharging unit, a first pull-down unit, a second pull-down unit and a control unit. The pull-up unit pulls up a gate signal according to a driving control voltage and a first clock. The buffer unit receives an input signal. The energy-store unit provides the driving control voltage through performing a charging process based on the input signal. The first pull-down unit pulls down the gate signal according to a control signal. The second pull-down unit pulls down the gate signal according to a second clock having a phase opposite to the first clock. The control unit generates the control signal based on the gate signal.

摘要翻译： 公开了一种高可靠性栅极驱动电路，用于分别向多个栅极线提供多个栅极信号。 栅极驱动电路包括多个移位寄存器级。 每个移位寄存器级包括上拉单元，能量存储单元，缓冲单元，放电单元，第一下拉单元，第二下拉单元和控制单元。 上拉单元根据驱动控制电压和第一个时钟上拉一个门信号。 缓冲单元接收输入信号。 能量存储单元通过基于输入信号进行充电处理来提供驱动控制电压。 第一个下拉单元根据控制信号拉下门信号。 第二下拉单元根据具有与第一时钟相反的相位的第二时钟来拉低门信号。 控制单元根据门信号产生控制信号。

公开(公告)号：US20080254578A1

公开(公告)日：2008-10-16

申请号：US11882539

申请日：2007-08-02

申请人： Chih-Jen Shih ,  Wen-Chun Yeh ,  Min-Che Ho ,  Wen-Chi Yang

发明人： Chih-Jen Shih ,  Wen-Chun Yeh ,  Min-Che Ho ,  Wen-Chi Yang

IPC分类号： H01L21/84

CPC分类号： H01L21/02686 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02675 ,  H01L27/1285

摘要： A method for fabricating thin film transistors is disclosed. An amorphous silicon film is formed on a substrated and selectively irradiated with a laser beam for lateral growth to form a plurality of polysilicon regions. The whole surface of the substrate is then oxidized and irradiated with exicer laser annealing.

摘要翻译： 公开了制造薄膜晶体管的方法。 一个非晶硅膜形成在一个底层上并选择性地用激光束照射以进行横向生长以形成多个多晶硅区域。 然后将基板的整个表面氧化并用激光退火进行照射。

公开(公告)号：US20070051956A1

公开(公告)日：2007-03-08

申请号：US11162159

申请日：2005-08-31

申请人： Chih-Jen Shih ,  Chun-Hsiang Fang ,  Te-Hua Teng ,  Chia-Chien Lu

发明人： Chih-Jen Shih ,  Chun-Hsiang Fang ,  Te-Hua Teng ,  Chia-Chien Lu

IPC分类号： H01L29/00

CPC分类号： H01L29/78645 ,  H01L29/78624

摘要： A thin film transistor having a substrate, a gate insulating layer, a double-gate structure, a first lightly doped region, and a second lightly doped region. The substrate has a source region and a drain region disposed on its opposite sides, a heavily doped region between source region and drain region, a first channel region between heavily doped region and source region and a second channel region between heavily doped region and drain region. The gate insulating layer covers the substrate. The double-gate structure has a first gate and a second gate disposed on gate insulating layer above the first and the second channel region, respectively. The first lightly doped region is disposed between second channel region and heavily doped region and the second lightly doped region between second channel region and drain region. The length of second lightly doped region is greater than that of first lightly doped region.

摘要翻译： 一种具有衬底，栅极绝缘层，双栅极结构，第一轻掺杂区和第二轻掺杂区的薄膜晶体管。 衬底具有设置在其相对侧上的源极区域和漏极区域，源极区域和漏极区域之间的重掺杂区域，重掺杂区域和源极区域之间的第一沟道区域以及重掺杂区域和漏极区域之间的第二沟道区域 。 栅极绝缘层覆盖基板。 双栅结构具有分别设置在第一和第二沟道区上方的栅极绝缘层上的第一栅极和第二栅极。 第一轻掺杂区域设置在第二沟道区域和重掺杂区域之间，第二轻掺杂区域设置在第二沟道区域和漏极区域之间。 第二轻掺杂区域的长度大于第一轻掺杂区域的长度。

公开(公告)号：US20070155135A1

公开(公告)日：2007-07-05

申请号：US11306899

申请日：2006-01-16

申请人： Yun-Pei Yang ,  Te-Hua Teng ,  Chih-Jen Shih ,  Chia-Chien Lu

发明人： Yun-Pei Yang ,  Te-Hua Teng ,  Chih-Jen Shih ,  Chia-Chien Lu

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/02686 ,  H01L21/0242 ,  H01L21/02422 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02672 ,  H01L27/1277

摘要： A method of fabricating a polysilicon layer is provided. A substrate having a front surface and a back surface is provided. A buffer layer, an amorphous layer and a cap layer are sequentially formed on the front surface of the substrate. The cap layer is patterned to form a patterned cap layer exposing a portion of the amorphous layer, wherein the exposed portion of the amorphous layer is a crystallization initial region. A metallic catalytic layer is formed on the patterned cap layer, wherein the metallic catalytic layer contacts with the crystallization initial region of the amorphous layer. A laser annealing process is performed through the back surface of the substrate so that the amorphous layer is crystallized and transformed into a polysilicon layer from the crystallization initial region.

摘要翻译： 提供一种制造多晶硅层的方法。 提供具有前表面和后表面的基板。 缓冲层，非晶层和盖层依次形成在基板的前表面上。 图案化盖层以形成暴露非晶层的一部分的图案化盖层，其中非晶层的暴露部分是结晶初始区域。 在图案化盖层上形成金属催化剂层，其中金属催化剂层与非晶层的结晶初始区域接触。 通过衬底的背面进行激光退火处理，使得非晶层从结晶初始区域结晶化并转变为多晶硅层。