公开(公告)号：US07177220B2

公开(公告)日：2007-02-13

申请号：US10841264

申请日：2004-05-07

Applicant: Chung-Cheng Chou ,  Chien-Hua Chuang

Inventor： Chung-Cheng Chou ,  Chien-Hua Chuang

IPC: G11C7/00

CPC classification number: G11C11/40626 ,  G11C11/406 ,  G11C2211/4061 ,  G11C2211/4068

Abstract: A method and system for DRAM refresh wherein the refresh rate is proportional to the current leakage of one or more sampling cells. The sampling cells selected are representative of the nominal leakage condition of the DRAM array and track the DRAM cell leakage rates, which are dependent upon manufacturing process variations, application influences, voltage variations and the temperature of the system, both locally and globally. As the current leakage through the DRAM increases, the refresh cycle repetition frequency increases and accordingly decreases for low leakage conditions. By adjusting the refresh rate in the manner described by the invention disclosed herein, the semiconductor conserves power by reducing unnecessary refresh cycles, generates the required delay between cycles without undue power consumption and provides a cost effective means that does not require external settings and calibration to optimize the refresh rate for the variations heretofore mentioned.

Abstract translation: 一种用于DRAM刷新的方法和系统，其中刷新率与一个或多个采样单元的电流泄漏成比例。 所选择的采样单元代表DRAM阵列的标称泄漏状态，并跟踪DRAM单元泄漏速率，这取决于本地和全局的制造工艺变化，应用影响，电压变化和系统的温度。 随着通过DRAM的电流泄漏增加，刷新周期重复频率增加并因此在低泄漏条件下降低。 通过以本文公开的本发明描述的方式调整刷新速率，半导体通过减少不必要的刷新周期来节省功率，在没有不必要的功耗的情况下产生周期之间所需的延迟，并且提供了不需要外部设置和校准的成本有效的手段 优化上述变化的刷新率。

公开(公告)号：US20050248755A1

公开(公告)日：2005-11-10

申请号：US10841264

申请日：2004-05-07

Applicant: Chung-Cheng Chou ,  Chien-Hua Chuang

Inventor： Chung-Cheng Chou ,  Chien-Hua Chuang

IPC: G01J1/42 ,  G11C11/406

CPC classification number: G11C11/40626 ,  G11C11/406 ,  G11C2211/4061 ,  G11C2211/4068

Abstract: A method and system for DRAM refresh wherein the refresh rate is proportional to the current leakage of one or more sampling cells. The sampling cells selected are representative of the nominal leakage condition of the DRAM array and track the DRAM cell leakage rates, which are dependent upon manufacturing process variations, application influences, voltage variations and the temperature of the system, both locally and globally. As the current leakage through the DRAM increases, the refresh cycle repetition frequency increases and accordingly decreases for low leakage conditions. By adjusting the refresh rate in the manner described by the invention disclosed herein, the semiconductor conserves power by reducing unnecessary refresh cycles, generates the required delay between cycles without undue power consumption and provides a cost effective means that does not require external settings and calibration to optimize the refresh rate for the variations heretofore mentioned.

Abstract translation: 一种用于DRAM刷新的方法和系统，其中刷新率与一个或多个采样单元的电流泄漏成比例。 所选择的采样单元代表DRAM阵列的标称泄漏状态，并跟踪DRAM单元泄漏速率，这取决于本地和全局的制造工艺变化，应用影响，电压变化和系统的温度。 随着通过DRAM的电流泄漏增加，刷新周期重复频率增加并因此在低泄漏条件下降低。 通过以本文公开的本发明描述的方式调整刷新速率，半导体通过减少不必要的刷新周期来节省功率，在没有不必要的功耗的情况下产生周期之间所需的延迟，并且提供了不需要外部设置和校准的成本有效的手段 优化上述变化的刷新率。