SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER WITH MULTIPLE SAMPLE CAPACITORS

    公开(公告)号:US20240187016A1

    公开(公告)日:2024-06-06

    申请号:US18098544

    申请日:2023-01-18

    CPC classification number: H03M1/466

    Abstract: A SAR ADC may include a plurality of capacitor networks, wherein each capacitor network of the a plurality of capacitor networks has a plurality of sampling capacitors for sampling over a plurality of sampling sub-phases an analog input signal to the SAR ADC and at least one non-sampling capacitor. The SAR ADC may also include a DAC comprising a plurality of sub-DACs including at least a first sub-DAC representing most significant bits of an output of the SAR ADC, wherein the output of the first sub-DAC is coupled to the sampling capacitors of the plurality of capacitor networks and a second sub-DAC representing bits of the output of the SAR ADC lesser in magnitude significance than those of the first sub-DAC, wherein the output of the second sub-DAC is coupled to a respective one of at least one non-sampling capacitor of each of the plurality of capacitor networks.

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