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    PARAMETER-INDEPENDENT RAMP SIGNAL GENERATION
    2.
    发明申请
    PARAMETER-INDEPENDENT RAMP SIGNAL GENERATION 审中-公开

    公开(公告)号：US20190379367A1

    公开(公告)日：2019-12-12

    申请号：US16431320

    申请日：2019-06-04

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Saraubh SINGH ,  Vamsikrishna PARUPALLI

    IPC: H03K4/50

    Abstract: A system may include a ramp generation circuit for generating a ramp waveform and comprising a first passive circuit element having an impedance pertinent to generation of the ramp waveform and a control circuit comprising a second passive circuit element which is impedance-correlated to the first passive circuit element. The control circuit may be configured to use the second passive circuit element to generate a control signal for controlling the ramp generation circuit, such that a correlation between the first passive circuit element and the second passive circuit element substantially cancels physical variations of the first passive circuit element and the second passive circuit element and use a control signal clock for generating the control signal that is related to a ramp generation clock for generating the ramp waveform such that a magnitude of the ramp waveform remains substantially independent of frequency of operation.

    REDUCING NOISE IN A CAPACITIVE SENSOR
    4.
    发明申请
    REDUCING NOISE IN A CAPACITIVE SENSOR 审中-公开

    公开(公告)号：US20190011291A1

    公开(公告)日：2019-01-10

    申请号：US15926276

    申请日：2018-03-20

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Vamsikrishna PARUPALLI ,  Zhong YOU ,  Gaurav AGARWAL ,  Vikrant ARUMUGAM ,  Johann G. GABORIAU ,  Nishant JAIN

    IPC: G01D5/24 ,  G01R27/26 ,  H04L27/144 ,  G01R29/26

    Abstract: A method for measuring a capacitive sensor output may include applying an excitation signal to a capacitor of the capacitive sensor which causes generation of a modulated signal from a baseband signal, wherein the excitation signal is of a carrier frequency which is higher than frequency content of the baseband signal, demodulating the modulated signal to generate an output signal representative of a capacitance of the capacitor wherein the demodulating is based, at least in part, on the excitation signal, determining whether noise in the modulated signal is caused by interference at approximately the carrier frequency, and in response to determining noise in the modulated signal is caused by interference at approximately the carrier frequency, modifying the carrier frequency to another frequency to reduce noise caused in the modulated signal by the interference.

    CALIBRATION OF CURRENT SENSE AMPLIFIER WITH COMMON-MODE REJECTION
    6.
    发明申请
    CALIBRATION OF CURRENT SENSE AMPLIFIER WITH COMMON-MODE REJECTION 审中-公开

    公开(公告)号：US20190293691A1

    公开(公告)日：2019-09-26

    申请号：US16354781

    申请日：2019-03-15

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Katy HOLLAND ,  Vamsikrishna PARUPALLI ,  Christian LARSEN ,  Graeme MACKAY

    IPC: G01R19/10 ,  H03F1/02 ,  H03F3/45

    Abstract: A method for calculating a calibration gain used for common-mode rejection in a current sensing system may include measuring a first value of a common-mode voltage associated with the current sensing system and a first output value of the current sensing system occurring at the first value of the common-mode voltage, measuring a second value of the common-mode voltage associated with the current sensing system and a second output value of the current sensing system occurring at the second value of the common-mode voltage, and based on a difference between the second output value of the current sensing system and the first output value of the current sensing system and a difference between the second value of the common-mode voltage and the first value of the common-mode voltage, calculating the calibration gain.

    SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER WITH MULTIPLE SAMPLE CAPACITORS
    7.
    发明公开
    SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER WITH MULTIPLE SAMPLE CAPACITORS 审中-公开

    公开(公告)号：US20240187016A1

    公开(公告)日：2024-06-06

    申请号：US18098544

    申请日：2023-01-18

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Vamsikrishna PARUPALLI ,  Mikel ASH ,  Jianping WEN ,  Melvin L. HAGGE

    IPC: H03M1/46

    CPC classification number: H03M1/466

    Abstract: A SAR ADC may include a plurality of capacitor networks, wherein each capacitor network of the a plurality of capacitor networks has a plurality of sampling capacitors for sampling over a plurality of sampling sub-phases an analog input signal to the SAR ADC and at least one non-sampling capacitor. The SAR ADC may also include a DAC comprising a plurality of sub-DACs including at least a first sub-DAC representing most significant bits of an output of the SAR ADC, wherein the output of the first sub-DAC is coupled to the sampling capacitors of the plurality of capacitor networks and a second sub-DAC representing bits of the output of the SAR ADC lesser in magnitude significance than those of the first sub-DAC, wherein the output of the second sub-DAC is coupled to a respective one of at least one non-sampling capacitor of each of the plurality of capacitor networks.

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