公开(公告)号：US20210111131A1

公开(公告)日：2021-04-15

申请号：US17028707

申请日：2020-09-22

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John PAVELKA ,  David PATTEN

IPC: H01L23/552 ,  H01L23/00

Abstract: A semiconductor device may include an integrated circuit die and a thin metal layer applied and conformed to one or more surfaces of the integrated circuit die in order to shield active circuitry of the integrated circuit die from light.

公开(公告)号：US20230088252A1

公开(公告)日：2023-03-23

申请号：US17993638

申请日：2022-11-23

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Craig MCADAM ,  Jonathan TAYLOR ,  Douglas MACFARLANE ,  John KERR ,  James MUNGER ,  John PAVELKA ,  Steven A. ATHERTON

IPC: H01L23/498 ,  H01L23/00

Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.

公开(公告)号：US20220246514A1

公开(公告)日：2022-08-04

申请号：US17245259

申请日：2021-04-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Craig MCADAM ,  Jonathan TAYLOR ,  Douglas MACFARLANE ,  John KERR ,  James MUNGER ,  John PAVELKA ,  Steven A. ATHERTON

IPC: H01L23/498 ,  H01L23/00

Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.