公开(公告)号：US20230079673A1

公开(公告)日：2023-03-16

申请号：US17472196

申请日：2021-09-10

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Vivek T. Bhat ,  Nariankadu D. Hemkumar

IPC: G06F11/36 ,  G06F9/445 ,  G06F9/30

Abstract: A system includes a memory programmed with multiple firmware images each having a distinct entry point, a processor, a writable hardware register initially seeded with an initial firmware image entry point address. A controller external to the processor, prior to an initial processor reset, reads the hardware register and causes the processor to begin fetching instructions at the initial firmware image entry point read from the hardware register. Prior to a subsequent reset, the external controller facilitates at least one transition to at least one of the multiple firmware images other than the initial firmware image by reading the entry point of the other firmware images from the hardware register and causing the processor to begin fetching instructions at the entry point of the other firmware images read from the hardware register.

公开(公告)号：US11899567B2

公开(公告)日：2024-02-13

申请号：US17472196

申请日：2021-09-10

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Vivek T. Bhat ,  Nariankadu D. Hemkumar

IPC: G06F11/36 ,  G06F9/445 ,  G06F9/30

CPC classification number: G06F11/3688 ,  G06F9/30101 ,  G06F9/44505 ,  G06F11/3684 ,  G06F11/3692

Abstract: A system includes a memory programmed with multiple firmware images each having a distinct entry point, a processor, a writable hardware register initially seeded with an initial firmware image entry point address. A controller external to the processor, prior to an initial processor reset, reads the hardware register and causes the processor to begin fetching instructions at the initial firmware image entry point read from the hardware register. Prior to a subsequent reset, the external controller facilitates at least one transition to at least one of the multiple firmware images other than the initial firmware image by reading the entry point of the other firmware images from the hardware register and causing the processor to begin fetching instructions at the entry point of the other firmware images read from the hardware register.