中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

17 records (took 0.017 seconds)

    MULTI-CHIP CAMERA CONTROLLER SYSTEM WITH INTER-CHIP COMMUNICATION
    1.
    发明申请
    MULTI-CHIP CAMERA CONTROLLER SYSTEM WITH INTER-CHIP COMMUNICATION 有权

    公开(公告)号：US20250168500A1

    公开(公告)日：2025-05-22

    申请号：US18916181

    申请日：2024-10-15

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Younes Djadi ,  Nariankadu D. Hemkumar ,  Sachin Deo ,  Daniel T. Bogard ,  Nathan Daniel Pozniak Buchanan ,  Eric B. Smith

    IPC: H04N23/661 ,  G01D5/14 ,  G03B13/36 ,  H04N23/60 ,  H04N23/66

    Abstract: A system for using actuators to position an image sensor and/or lens based on position data of the image sensor and/or lens sensed by position sensors includes a primary camera controller device comprising sensor inputs that receive first sensor data from the position sensors and control outputs that drive first control data to the actuators, at least one secondary camera controller device comprising sensor inputs that receive second sensor data from the position sensors and control outputs that drive second control data to the actuators, and at least one communication link connecting the primary camera controller device and the at least one secondary camera controller device. The secondary camera controller device sends the second sensor data to the primary camera controller device via the communication link. The primary camera controller device processes the first and second sensor data to generate the first control data.

    System with dynamically selectable firmware image sequencing for production test, debug, prototyping
    2.
    发明授权
    System with dynamically selectable firmware image sequencing for production test, debug, prototyping 有权

    公开(公告)号：US12169720B2

    公开(公告)日：2024-12-17

    申请号：US17957708

    申请日：2022-09-30

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Nariankadu D. Hemkumar ,  Christopher Jackson ,  Younes Djadi ,  Nathan Daniel Pozniak Buchanan

    IPC: G06F9/4401 ,  G06F8/65 ,  G06F9/38

    Abstract: A system has a memory programmed with multiple firmware images each having an associated distinct entry point, a processor, a writable hardware register, and a controller external to the processor that, prior to each reset of a sequence of resets of the processor, reads the entry point of a firmware image from the hardware register and causes the processor to begin fetching instructions at the entry point read from the hardware register. The firmware images include boot, mission mode, and at least one other firmware image. The memory may be writeable with a modifiable version of a post-production mission mode, debug, prototype, or patched ROM firmware image. A second controller writes a second entry point to the hardware register prior to an initial reset such that the external controller reads the second entry point and causes fetching instructions at the second entry point rather than the initial entry point.

    System and method for providing increased number of time synchronized outputs by using communicating primary and secondary devices
    3.
    发明授权
    System and method for providing increased number of time synchronized outputs by using communicating primary and secondary devices 有权

    公开(公告)号：US12158687B2

    公开(公告)日：2024-12-03

    申请号：US17320528

    申请日：2021-05-14

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Sachin Deo ,  Nariankadu D. Hemkumar ,  Akhilesh Persha ,  Younes Djadi

    IPC: G06F1/10 ,  G03B5/04 ,  G03B13/36 ,  G06F1/12

    Abstract: A system includes primary and secondary devices (e.g., camera controllers that drive voice coil motors) each having respective outputs and a communication link. The primary device includes first and second hardware timers, each of which expires at a time derived from a periodic control loop trigger. At first timer expiration, the primary transmits first updated values to the secondary. At second timer expiration, primary device hardware picks up and applies second updated values to the primary device outputs. In response to receiving the first updated values from the primary device, the secondary device applies the received first updated values to its outputs. The primary/secondary device combination provide a sufficient number of total outputs that they could not individually provide and further synchronize the outputs with small skew through the timers, which are programmable to also accommodate processing of inputs (e.g., from voice coil motor sensors) to compute the outputs.

    MULTI-CHIP CAMERA CONTROLLER SYSTEM WITH INTER-CHIP COMMUNICATION
    7.
    发明申请
    MULTI-CHIP CAMERA CONTROLLER SYSTEM WITH INTER-CHIP COMMUNICATION 有权

    公开(公告)号：US20220329725A1

    公开(公告)日：2022-10-13

    申请号：US17737615

    申请日：2022-05-05

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Younes Djadi ,  Nariankadu D. Hemkumar ,  Sachin Deo ,  Daniel T. Bogard ,  Nathan Daniel Pozniak Buchanan ,  Eric B. Smith

    IPC: H04N5/232

    Abstract: A system for using actuators to control an image sensor and/or lens based on sensor data received from position sensors and position information for the image sensor and/or lens received from a host processor includes a primary camera controller device, at least one secondary camera controller device, and at least one communication link connecting the primary camera controller device and the secondary camera controller device. The primary camera controller device processes the received sensor data and the received position information to generate control data, sends a secondary portion of the control data to the secondary camera controller device via the communication link, and drives a primary portion of the control data to the actuators. The secondary camera controller device drives the received secondary portion of the control data to the actuators concurrently with the primary camera controller device driving the primary portion of the control data to the actuators.

    MULTI-CHIP CAMERA CONTROLLER SYSTEM WITH INTER-CHIP COMMUNICATION
    8.
    发明申请
    MULTI-CHIP CAMERA CONTROLLER SYSTEM WITH INTER-CHIP COMMUNICATION 有权

    公开(公告)号：US20220321765A1

    公开(公告)日：2022-10-06

    申请号：US17737673

    申请日：2022-05-05

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Younes Djadi ,  Nariankadu D. Hemkumar ,  Sachin Deo ,  Daniel T. Bogard ,  Nathan Daniel Pozniak Buchanan ,  Eric B. Smith

    IPC: H04N5/232 ,  G01D5/14 ,  G03B13/36

    Abstract: A system for using actuators to control an image sensor and/or lens based on sensor data received from position sensors and based on position information for the image sensor and/or lens received from a host processor includes a primary camera controller device, at least one secondary camera controller device, and at least one communication link connecting the primary camera controller device and the at least one secondary camera controller device. The primary and secondary camera controller devices receive respective primary and secondary sensor data from the position sensors, send the respective primary and secondary sensor data to the other camera controller device via the communication link, process the primary and secondary sensor data and the position information to generate respective primary and secondary control data, and drive the respective primary and secondary control data to the actuators concurrently.

    Flexible, non-blocking asynchronous transfer of time-variant atomic data
    9.
    发明授权
    Flexible, non-blocking asynchronous transfer of time-variant atomic data 有权

    公开(公告)号：US11288193B2

    公开(公告)日：2022-03-29

    申请号：US16404323

    申请日：2019-05-06

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Nathan Daniel Pozniak Buchanan ,  Nariankadu D. Hemkumar ,  Sachin Deo

    IPC: G06F12/0806 ,  H04N5/232 ,  G06F9/54

    Abstract: A system for atomically transferring vectors of data from a transmitter of the vectors of data to a receiver of the vectors of data may include a plurality of memory buffers configured to store the vectors of the data, each buffer configured to store one vector of the vectors of data at a time, the plurality of memory buffers comprising at least three memory buffers and a controller for controlling the plurality of memory buffers. The controller may be configured to, responsive to a condition for transferring information represented by the vectors of data to the receiver, determine which of the plurality of buffers from which the receiver may receive most-recently updated information completely written to the plurality of buffers by the transmitter. The controller may further be configured to, responsive to a condition for updating information represented by the vectors of data, determine which of the plurality of buffers for the transmitter to write updated information without blocking atomic receipt by the receiver of information from a most-recently updated buffer.

Patent Agency Ranking