公开(公告)号：US11322465B2

公开(公告)日：2022-05-03

申请号：US16897036

申请日：2020-06-09

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Kathryn R. Holland ,  Marc L. Tarabbia ,  Yaoyu Pang ,  Alexander Barr

IPC: H01L23/00

Abstract: A method may include forming a metal pattern in a metal layer of a fabricated integrated circuit device and under a target bump of the fabricated integrated circuit device, wherein the metal pattern has an inner shape and an outer field such that a void space in the metal layer is created between the inner shape and the outer field and approximately centering the void space on an outline of an under-bump metal formed under the target bump with a keepout distance from the inner shape and the outer field on either side of the outline such that the metal minimizes local variations in mechanical stress on underlying structures within the fabricated integrated circuit device.

公开(公告)号：US11373968B2

公开(公告)日：2022-06-28

申请号：US16857606

申请日：2020-04-24

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Yaoyu Pang ,  Steven A. Atherton

IPC: H01L23/00 ,  H01L23/52

Abstract: A semiconductor die may be coupled to a printed circuit board using a solder ball. The semiconductor die comprises a redistribution layer formed above a semiconductor chip, a polymer layer formed on the redistribution layer, and an Under Bump Metallurgy (UBM) layer formed on the polymer layer. The polymer layer comprises a plurality of vias, which electrically couple the UBM layer to the redistribution layer. The entire UBM layer may be deposited with a continuously flat upper surface for coupling to the solder ball. The plurality of vias may be positioned such that they are centered on a point that is not central to the UBM layer.