公开(公告)号：US20220124017A1

公开(公告)日：2022-04-21

申请号：US17075485

申请日：2020-10-20

Applicant: Cisco Technology, Inc.

Inventor： Padmanab Pathikonda ,  Rishi Chhibber ,  Roshan Lal ,  Lakshmi Priya Sarma ,  Vinay Narayana Rai ,  Akash Garg

IPC: H04L12/26 ,  H04J3/06

Abstract: This disclosure describes methods to process timing information of flows in a network. One or more processors determine a latency associated with each of one or more packets of a flow passing through a device. The one or more processors determine that the latency is greater than a baseline latency, and the one or more processors provide a message indicating at least the flow and that the latency is greater than the baseline latency.

公开(公告)号：US11916770B2

公开(公告)日：2024-02-27

申请号：US17075485

申请日：2020-10-20

Applicant: Cisco Technology, Inc.

Inventor： Padmanab Pathikonda ,  Rishi Chhibber ,  Roshan Lal ,  Lakshmi Priya Sarma ,  Vinay Narayana Rai ,  Akash Garg

IPC: H04L43/087 ,  H04J3/06 ,  H04L43/065

CPC classification number: H04L43/087 ,  H04J3/0661 ,  H04L43/065

Abstract: This disclosure describes methods to process timing information of flows in a network. One or more processors determine a latency associated with each of one or more packets of a flow passing through a device. The one or more processors determine that the latency is greater than a baseline latency, and the one or more processors provide a message indicating at least the flow and that the latency is greater than the baseline latency.