公开(公告)号：US09520178B2

公开(公告)日：2016-12-13

申请号：US14831008

申请日：2015-08-20

Applicant: Cisco Technology, Inc.

Inventor： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen

IPC: G11C7/22 ,  G11C11/419 ,  G11C11/412 ,  G11C11/413 ,  G11C8/16

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413

Abstract: Static random access memory (SRAM) circuits are used in most digital integrated circuits to store representations of data bits. To handle multiple concurrent memory requests, an efficient dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true/data side and the false/data-complement side of the SRAM bit cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two independent read operations in a single cycle using spatial domain multiplexing. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the SRAM bit cell.

Abstract translation: 在大多数数字集成电路中使用静态随机存取存储器（SRAM）电路来存储数据位的表示。 为了处理多个并发存储器请求，提出了一种高效的双端口六晶体管（6T）SRAM位单元。 双端口6T SRAM单元使用独立的字线和位线，使得可以独立地访问SRAM位单元的真/数据侧和伪/数据补码侧。 单端读取允许两个独立的字线和位线使用空间域复用在单个周期中处理两个独立的读操作。 通过调整在执行写入时提供给存储单元的VDD电源电压，使得可以使用单个字线和位线对将逻辑“0”或逻辑“1”写入到 SRAM位单元。

公开(公告)号：US09147466B2

公开(公告)日：2015-09-29

申请号：US14274518

申请日：2014-05-09

Applicant: Cisco Technology, Inc.

Inventor： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen

IPC: G11C7/22 ,  G11C11/419 ,  G11C11/412 ,  G11C11/413 ,  G11C8/16

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413

Abstract: Static random access memory (SRAM) circuits are used in most digital integrated circuits to store representations of data bits. To handle multiple concurrent memory requests, an efficient dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true/data side and the false/data-complement side of the SRAM bit cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two independent read operations in a single cycle using spatial domain multiplexing. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the SRAM bit cell. Thus, spatial domain multiplexing with a voltage assist allows single-ended writes to handle two independent write operations to be handled in a single cycle. A write buffer may be added to the memory system to prevent conflicts and thus enable concurrent read operations and write operations in a single cycle.

Abstract translation: 在大多数数字集成电路中使用静态随机存取存储器（SRAM）电路来存储数据位的表示。 为了处理多个并发存储器请求，提出了一种高效的双端口六晶体管（6T）SRAM位单元。 双端口6T SRAM单元使用独立的字线和位线，使得可以独立地访问SRAM位单元的真/数据侧和伪/数据补码侧。 单端读取允许两个独立的字线和位线使用空间域复用在单个周期中处理两个独立的读操作。 通过调整在执行写入时提供给存储单元的VDD电源电压，使得可以使用单个字线和位线对将逻辑“0”或逻辑“1”写入到 SRAM位单元。 因此，具有电压辅助的空间域复用允许单端写入来处理在单个周期中处理的两个独立的写操作。 可以将写缓冲器添加到存储器系统以防止冲突，从而在单个周期中实现并行读取操作和写入操作。

公开(公告)号：US09390212B2

公开(公告)日：2016-07-12

申请号：US14702971

申请日：2015-05-04

Applicant: Cisco Technology, Inc.

Inventor： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen ,  Sanjeev Joshi ,  Adam Kablanian

IPC: G11C11/00 ,  G06F17/50 ,  G11C11/419

CPC classification number: G06F17/505 ,  G06F17/5072 ,  G11C7/10 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419

Abstract: Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.

公开(公告)号：US20150357030A1

公开(公告)日：2015-12-10

申请号：US14831008

申请日：2015-08-20

Applicant: Cisco Technology, Inc.

Inventor： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413

Abstract: Static random access memory (SRAM) circuits are used in most digital integrated circuits to store representations of data bits. To handle multiple concurrent memory requests, an efficient dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true/data side and the false/data-complement side of the SRAM bit cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two independent read operations in a single cycle using spatial domain multiplexing. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the SRAM bit cell.

Abstract translation: 在大多数数字集成电路中使用静态随机存取存储器（SRAM）电路来存储数据位的表示。 为了处理多个并发存储器请求，提出了一种高效的双端口六晶体管（6T）SRAM位单元。 双端口6T SRAM单元使用独立的字线和位线，使得可以独立地访问SRAM位单元的真/数据侧和伪/数据补码侧。 单端读取允许两个独立的字线和位线使用空间域复用在单个周期中处理两个独立的读操作。 通过调整在执行写入时提供给存储单元的VDD电源电压，使得可以使用单个字线和位线对将逻辑“0”或逻辑“1”写入到 SRAM位单元。

公开(公告)号：US20150234950A1

公开(公告)日：2015-08-20

申请号：US14702971

申请日：2015-05-04

Applicant: Cisco Technology, Inc.

Inventor： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen ,  Sanjeev Joshi ,  Adam Kablanian

IPC: G06F17/50 ,  G11C11/419

CPC classification number: G06F17/505 ,  G06F17/5072 ,  G11C7/10 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419

Abstract: Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.

Abstract translation: 现代数字集成电路中通常需要多端口存储器电路来存储数据。 多端口存储器电路允许多个存储器用户同时访问相同的存储器单元。 多端口存储器电路通常是为了获得最佳性能而定制设计的，或者通过用于快速设计的逻辑综合工具来合成。 然而，创建多端口存储器的这两个选项为集成电路设计师提供了一个明显的选择：投入大量的时间和金钱来定制设计高效的多端口存储器系统，或允许逻辑综合工具低效地创建多端口存储器。 公开了一种中间解决方案，其允许使用标准电路单元组件和寄存器传输级硬件设计语言代码来大量创建有效的多端口存储器阵列。