公开(公告)号：US20090284283A1

公开(公告)日：2009-11-19

申请号：US12121149

申请日：2008-05-15

申请人： Claudio Alonso Denegri

发明人： Claudio Alonso Denegri

IPC分类号： H03K19/20 ,  H03K19/0185

CPC分类号： H03K19/018514 ,  H03K5/1515 ,  H03K2005/00136 ,  H03M1/0863 ,  H03M1/742

摘要： A ratio asymmetric inverter has a signal input, signal output, first and second power inputs, pullup and pulldown transistors, and at least one delay element. The pullup transistor has a gate terminal, a source terminal coupled to the first power input, and a drain terminal coupled to the signal output. The pulldown transistor has a gate terminal, a drain terminal coupled to the signal output, and a source terminal coupled to the second power input. The signal input is respectively coupled to the gate terminals of the pullup transistor and the pulldown transistor via first and second signal paths. The at least one delay element is included in only one of the first and second signal paths, to impart a longer propagation delay to the one of the first and second signal paths.

摘要翻译： 比例非对称逆变器具有信号输入，信号输出，第一和第二功率输入，上拉和下拉晶体管以及至少一个延迟元件。 上拉晶体管具有栅极端子，耦合到第一电力输入端的源极端子和耦合到信号输出端的漏极端子。 下拉晶体管具有栅极端子，耦合到信号输出的漏极端子和耦合到第二电力输入端的源极端子。 信号输入分别经由第一和第二信号路径耦合到上拉晶体管和下拉晶体管的栅极端子。 至少一个延迟元件仅包括在第一和第二信号路径中的一个中，以向第一和第二信号路径中的一个施加更长的传播延迟。