摘要:
A circuit for detecting a signal transition on an input signal includes a mirror delay circuit and an input blocking circuit to prevent signal glitches or undesired signal pulses from being passed to the output signal node, thereby preventing signal distortions from being detected as a valid signal transition. The input transition detection circuit generates stable and correct transition detection pulses having a consistent pulse width.
摘要:
A Delay-Locked Loop (DLL) uses a delay line to delay a first signal by a “delay time”, thereby generating a second signal. A capacitor is charged at a first rate starting at a first edge of first signal and continuing until an edge of the second signal. The capacitor is then discharged at a second rate until another edge of the first signal. A control loop controls the delay time such that the amount the capacitor is charged is the same as the amount the capacitor is discharged. The delay time is constant and is substantially independent of variations in the duty cycle of the first signal. In one example, duty cycle distortion cancellation is accomplished by changing the first rate proportionally with respect to changes in first signal duty cycle. In another example, the first and second rates are independent of the duty cycle of the first signal.
摘要:
A semiconductor integrated circuit includes a multiplexer, a signal generating circuit, a control circuit, m inverters, n two-input NOR circuits, and cascade connected n two-shift registers. The control circuit generates a control signal in the disable state in a normal operation in which the clock signal is supplied. The control circuit generates a control signal in an enable state in the other-than-normal operation in which a higher voltage source voltage is supplied while the clock signal is not supplied. The multiplexer receives the clock signal and a low-frequency signal outputted from the signal generating circuit. The multiplexer supplies the clock signal to the sequence of the inverters upon receipt of the control signal in the disable state, and supplies the low-frequency signal to the sequence of the inverters upon receipt of the control signal in the enable state.
摘要:
A rising edge or a falling edge is finely adjusted, or a dead time and a period are adjusted with high accuracy. A waveform processing circuit includes: an integration circuit 11 receiving a rectangular or substantially-rectangular pulse and outputting a gradually increasing or decreasing signal obtained by integrating the pulse signal; a reference signal output circuit 12 outputting a constant value or a varying value as a reference signal; and a comparison circuit 13 comparing the output of the integration circuit with the output of the reference signal output circuit and outputting a pulse rising or falling at a timing when the difference between the outputs varies.
摘要:
According to some embodiments, a method and system are provided to receive a clock input at a first clock adjustment tuner, receive the clock input at a second clock adjustment tuner, output a tuned inverted rising clock signal via the first clock adjustment tuner, output a tuned inverted falling clock signal via the second clock adjustment tuner, receive the inverted rising clock signal and the inverted falling clock signal at a clock synchronizer, output a synchronized tuned clock signal via the clock synchronizer, receive the synchronized tuned clock signal at a third clock adjustment tuner, and output a tuned clock signal. The first clock adjustment tuner and the second clock adjustment tuner provide coarser adjustments than the third clock adjustment tuner.
摘要:
A ratio asymmetric inverter has a signal input, signal output, first and second power inputs, pullup and pulldown transistors, and at least one delay element. The pullup transistor has a gate terminal, a source terminal coupled to the first power input, and a drain terminal coupled to the signal output. The pulldown transistor has a gate terminal, a drain terminal coupled to the signal output, and a source terminal coupled to the second power input. The signal input is respectively coupled to the gate terminals of the pullup transistor and the pulldown transistor via first and second signal paths. The at least one delay element is included in only one of the first and second signal paths, to impart a longer propagation delay to the one of the first and second signal paths.
摘要:
The present invention discloses a floating body architecture CMOSFET inverter with body biasing inverters added for controlling the delay time of the inverter. At least one body biasing inverter is connected between the main inverter's input and the body terminals of the FETs of the inverter. By supplying a representation of the input voltage to the body terminals of the p-channel and n-channel FETs, the preferred embodiment of the present invention is able to control the history dependent delay time associated with the variable source-to-body voltages in floating body CMOSFET inverters. The delay time is minimized by adding an odd number of body biasing inverter stages into the main inverter circuit. The delay time can also be maximized by adding an even number of body biasing inverter stages into the circuit.
摘要:
Circuit techniques provide different trip points for a rising-edge and for a falling-edge input to a logic gate. Adjustment of the gate trip point for a rising-edge input may be independently adjusted to that for the falling-edge input, and vice versa. Different circuit topologies are provided for delay chains on integrated circuits. Each implementation allows flexibility in delay elements through metal options to allow modifying delay chain delays with simple metal-only layout changes. Delay chains are used in integrated circuits to produce either a constant delay or to track another circuit delay.
摘要:
A method and apparatus for matching rise time and fall time in two differential signals. The apparatus includes a system that includes an scaled summer, a reference voltage generator, a comparator, and a storage device. The scaled summer receives two input signals and generates an instantaneous scaled sum of the two input signals. The reference voltage generator generating a reference voltage. The comparator compares the scaled summer output signal and the reference voltage and generates a comparison signal. The storage device stores the comparison signal. The stored comparison signal is usable to adjust one of the rise time and the fall time of both of the two input signals to match one of the fall time and the rise time of the two input signals.
摘要:
Three delay lines may have common characteristics. The first delay line delays the rising edge of an input signal and a first inverter inverts this signal to provide a falling edge. A second inverter inverts the rising edge of the input signal to produce a falling edge which is introduced to the second delay line in a second path with the second inverter. The signals from the two paths may be introduced to a comparator which produces a control signal having logic levels dependent upon the relative times that the falling edges occur for the signals in the two paths. For example, the control signal may have the first logic level when the falling edge occurs first in the first path and the control signal may have the second logic level when the falling edge occurs first in the second path. The voltage from a charge pump is adjusted in accordance with the logic level of the control signal. This voltage is introduced to the first and second delay lines to adjust their delay to minimize the time difference in the falling edges of the signals from these lines. This voltage is also introduced to the third delay line to adjust its delay in accordance with the adjustments in the delays in the first and second lines. In this way, the third delay line provides the same time for rising edges and falling edges in data signals introduced to the line.