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公开(公告)号：US11258460B2
公开(公告)日：2022-02-22
申请号：US17344689
申请日：2021-06-10
Applicant: Codelucida, Inc.
Inventor： David Declercq , Benedict J. Reynwar , Vamsi Krishna Yella
Abstract: This invention presents a method and the corresponding hardware apparatus for decoding LDPC codes using a vertical layered (VL) iterative message passing algorithm. The invention operates on quasi-cyclic LDPC (QC-LDPC) codes, for which the non-zero circulant permutation matrices (CPMs) are placed at specific locations in the parity-check matrix of the codes, forming concentrated clusters of CPMs. The purpose of the invention is to take advantage of the organization of CPMs in clusters in order to derive a specific hardware architecture, consuming less power than the classical VL decoders. This is achieved by minimizing the number of read and write accesses to the main memories of the design.
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公开(公告)号：US10778251B2
公开(公告)日：2020-09-15
申请号：US16530944
申请日：2019-08-02
Applicant: Codelucida, Inc.
Inventor： David Declercq , Bane Vasic , Benedict J. Reynwar
Abstract: A method and apparatus for encoding low-density parity check codes uses parity check matrices composed of circulant blocks. The apparatus operates on a parity check matrix of a judiciously designed block structure, which permits low cost hardware implementation, and high encoding throughput.
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公开(公告)号：US20220255560A1
公开(公告)日：2022-08-11
申请号：US17676065
申请日：2022-02-18
Applicant: Codelucida, Inc.
Inventor： David Declercq , Benedict J. Reynwar , Vamsi Krishna Yella
IPC: H03M13/11
Abstract: This invention presents a method and the corresponding hardware apparatus for decoding LDPC codes using a vertical layered (VL) iterative message passing algorithm. The invention operates on quasi-cyclic LDPC (QC-LDPC) codes, for which the non-zero circulant permutation matrices (CPMs) are placed at specific locations in the parity-check matrix of the codes, forming concentrated clusters of CPMs. The purpose of the invention is to take advantage of the organization of CPMs in clusters in order to derive a specific hardware architecture, consuming less power than the classical VL decoders. This is achieved by minimizing the number of read and write accesses to the main memories of the design.
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公开(公告)号：US10530392B2
公开(公告)日：2020-01-07
申请号：US16049724
申请日：2018-07-30
Applicant: Codelucida, Inc.
Inventor： Benedict J. Reynwar , David Declercq , Shiva Kumar Planjery
Abstract: This invention presents a method and apparatus for vertical layered finite alphabet iterative decoding of low-density parity-check codes (LDPC) which operate on parity check matrices that consist of blocks of sub-matrices. The iterative decoding involves passing messages between variable nodes and check nodes of the Tanner graph that associated with one or more sub-matrices constitute decoding blocks, and the messages belong to a finite alphabet. Various embodiments for the method and apparatus of the invention are presented that can achieve very high throughputs with low hardware resource usage and power.
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公开(公告)号：US11496155B2
公开(公告)日：2022-11-08
申请号：US17224064
申请日：2021-04-06
Applicant: Codelucida, Inc.
Inventor： David Declercq , Vamsi Krishna Yella , Benedict J. Reynwar
Abstract: A method and apparatus for decoding quasi-cyclic LDPC codes using a vertical layered iterative message passing algorithm. The algorithm of the method improves the efficiency of the check node update by using one or more additional magnitudes, predicted with predictive magnitude maps, for the computation of messages and update of the check node states. The method allows reducing the computational complexity, as well as the storage requirements, of the processing units in the check node update. Several embodiments for the apparatus are presented, using one or more predictive magnitude maps, targeting significant savings in resource usage and power consumption, while minimizing the impact on the error correction performance loss.
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Patent Agency Ranking
公开(公告)号：US20200220557A1
公开(公告)日：2020-07-09
申请号：US16735641
申请日：2020-01-06
Applicant: Codelucida, Inc.
Inventor： Benedict J. Reynwar , David Declercq , Shiva Kumar Planjery
Abstract: This invention presents a method and apparatus for vertical layered finite alphabet iterative decoding of low-density parity-check codes (LDPC) which operate on parity check matrices that consist of blocks of sub-matrices. The iterative decoding involves passing messages between variable nodes and check nodes of the Tanner graph that associated with one or more sub-matrices constitute decoding blocks, and the messages belong to a finite alphabet. Various embodiments for the method and apparatus of the invention are presented that can achieve very high throughputs with low hardware resource usage and power.
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公开(公告)号：US20200044667A1
公开(公告)日：2020-02-06
申请号：US16530944
申请日：2019-08-02
Applicant: Codelucida, Inc.
Inventor： David Declercq , Bane Vasic , Benedict J. Reynwar
Abstract: This disclosure presents a method and the corresponding hardware apparatus for encoding low-density parity check codes whose parity check matrices are composed of circulant blocks. The encoder operates on a parity check matrix of a judiciously designed block structure, which permits low cost hardware implementation, and high encoding throughput.
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公开(公告)号：US11381255B2
公开(公告)日：2022-07-05
申请号：US16735641
申请日：2020-01-06
Applicant: Codelucida, Inc.
Inventor： Benedict J. Reynwar , David Declercq , Shiva Kumar Planjery
Abstract: This invention presents a method and apparatus for vertical layered finite alphabet iterative decoding of low-density parity-check codes (LDPC) which operate on parity check matrices that consist of blocks of sub-matrices. The iterative decoding involves passing messages between variable nodes and check nodes of the Tanner graph that associated with one or more sub-matrices constitute decoding blocks, and the messages belong to a finite alphabet. Various embodiments for the method and apparatus of the invention are presented that can achieve very high throughputs with low hardware resource usage and power.
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公开(公告)号：US20220085828A1
公开(公告)日：2022-03-17
申请号：US17224064
申请日：2021-04-06
Applicant: Codelucida, Inc.
Inventor： David Declercq , Vamsi Krishna Yella , Benedict J. Reynwar
Abstract: A method and apparatus for decoding quasi-cyclic LDPC codes using a vertical layered iterative message passing algorithm. The algorithm of the method improves the efficiency of the check node update by using one or more additional magnitudes, predicted with predictive magnitude maps, for the computation of messages and update of the check node states. The method allows reducing the computational complexity, as well as the storage requirements, of the processing units in the check node update. Several embodiments for the apparatus are presented, using one or more predictive magnitude maps, targeting significant savings in resource usage and power consumption, while minimizing the impact on the error correction performance loss.
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公开(公告)号：US20210391872A1
公开(公告)日：2021-12-16
申请号：US17344689
申请日：2021-06-10
Applicant: Codelucida, Inc.
Inventor： David Declercq , Benedict J. Reynwar , Vamsi Krishna Yella
IPC: H03M13/11
Abstract: This invention presents a method and the corresponding hardware apparatus for decoding LDPC codes using a vertical layered (VL) iterative message passing algorithm. The invention operates on quasi-cyclic LDPC (QC-LDPC) codes, for which the non-zero circulant permutation matrices (CPMs) are placed at specific locations in the parity-check matrix of the codes, forming concentrated clusters of CPMs. The purpose of the invention is to take advantage of the organization of CPMs in clusters in order to derive a specific hardware architecture, consuming less power than the classical VL decoders. This is achieved by minimizing the number of read and write accesses to the main memories of the design.
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