QUADRATURE DEMODULATOR FOR A VERY HIGH BIT RATE RFID RECEIVER
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    发明申请
    QUADRATURE DEMODULATOR FOR A VERY HIGH BIT RATE RFID RECEIVER 有权
    用于非常高的位速率RFID接收器的平衡解调器

    公开(公告)号:US20170012676A1

    公开(公告)日:2017-01-12

    申请号:US15204310

    申请日:2016-07-07

    IPC分类号: H04B5/00 H04L27/227

    摘要: A quadrature demodulator not requiring analogue mixers. The demodulation is made using a first integrator and a second integrator which are controlled by square logic signals at twice the frequency of the carrier, the received signal being alternatively integrated by the first integrator and the second integrator over periods of time equal to a quarter period of time of the carrier frequency. The samples of the first and second integrators are sampled and subtracted from each other. The successive samples are combined in a first and a second combining module for providing in-phase and quadrature component samples. This demodulator can further be provided with a synchronization module IQ and a symbol synchronization module.

    摘要翻译: 不需要模拟混频器的正交解调器。 使用由载波频率的两倍的平方逻辑信号控制的第一积分器和第二积分器进行解调,接收到的信号由等于四分之一周期的时间段由第一积分器和第二积分器交替地集成 的载波频率的时间。 对第一和​​第二积分器的样本进行采样并相减。 连续样本在第一和第二组合模块中组合以提供同相和正交分量样本。 该解调器还可以设置有同步模块IQ和符号同步模块。