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公开(公告)号：US11693662B2
公开(公告)日：2023-07-04
申请号：US16743257
申请日：2020-01-15
申请人： Cornami Inc.
CPC分类号： G06F9/3812 , G06F7/4806 , G06F8/4436 , G06F17/142
摘要： Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.
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2.发明申请公开(公告)号：US20220179823A1
公开(公告)日：2022-06-09
申请号：US17681163
申请日：2022-02-25
申请人： Cornami Inc.
摘要： Systems and methods for reconfiguring a reduced instruction set computer processor architecture are disclosed. Exemplary implementations may: provide a primary processing core consisting of a RISC processor; provide a node wrapper associated with each of the plurality of secondary cores, the node wrapper comprising access memory associates with each secondary core, and a load/unload matrix associated with each secondary core; operate the architecture in a manner in which, for at least one core, data is read from and written to the at least cache memory in a control-centric mode; the secondary cores are selectively partitioned to operate in a streaming mode wherein data streams out of the corresponding secondary core into the main memory and other ones of the plurality of secondary cores.
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公开(公告)号：US20200213079A1
公开(公告)日：2020-07-02
申请号：US16743257
申请日：2020-01-15
申请人： Cornami Inc.
发明人： Mache Kreeger , Tianfang Liu , Frederick Furtek , Paul L. Master
摘要： Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.
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公开(公告)号：US20230350684A1
公开(公告)日：2023-11-02
申请号：US18205929
申请日：2023-06-05
申请人： Cornami Inc.
CPC分类号： G06F9/3812 , G06F7/4806 , G06F17/142 , G06F8/4436
摘要： Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.
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公开(公告)号：US10318260B2
公开(公告)日：2019-06-11
申请号：US15943032
申请日：2018-04-02
申请人： Cornami, Inc
发明人： Frederick Furtek , Paul Master
摘要： A method and system of compiling and linking source stream programs for efficient use of multi-node devices. The system includes a compiler, a linker, a loader and a runtime component. The process converts a source code stream program to a compiled object code that is used with a programmable node based computing device having a plurality of processing nodes coupled to each other. The programming modules include stream statements for input values and output values in the form of sources and destinations for at least one of the plurality of processing nodes and stream statements that determine the streaming flow of values for the at least one of the plurality of processing nodes. The compiler converts the source code stream based program to object modules, object module instances and executables. The linker matches the object module instances to at least one of the multiple cores. The loader loads the tasks required by the object modules in the nodes and configure the nodes matched with the object module instances. The runtime component runs the converted program.
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6.发明授权公开(公告)号：US11294851B2
公开(公告)日：2022-04-05
申请号：US15970915
申请日：2018-05-04
申请人： Cornami Inc.
摘要： Systems and methods for reconfiguring a reduced instruction set computer processor architecture are disclosed. Exemplary implementations may: provide a primary processing core consisting of a RISC processor; provide a node wrapper associated with each of the plurality of secondary cores, the node wrapper comprising access memory associates with each secondary core, and a load/unload matrix associated with each secondary core; operate the architecture in a manner in which, for at least one core, data is read from and written to the at least cache memory in a control-centric mode; the secondary cores are selectively partitioned to operate in a streaming mode wherein data streams out of the corresponding secondary core into the main memory and other ones of the plurality of secondary cores.
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7.发明申请公开(公告)号：US20190340152A1
公开(公告)日：2019-11-07
申请号：US15970915
申请日：2018-05-04
申请人： Cornami Inc.
摘要： Systems and methods for reconfiguring a reduced instruction set computer processor architecture are disclosed. Exemplary implementations may: provide a primary processing core consisting of a RISC processor; provide a node wrapper associated with each of the plurality of secondary cores, the node wrapper comprising access memory associates with each secondary core, and a load/unload matrix associated with each secondary core; operate the architecture in a manner in which, for at least one core, data is read from and written to the at least cache memory in a control-centric mode; the secondary cores are selectively partitioned to operate in a streaming mode wherein data streams out of the corresponding secondary core into the main memory and other ones of the plurality of secondary cores.
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公开(公告)号：US20240069918A1
公开(公告)日：2024-02-29
申请号：US17893993
申请日：2022-08-23
申请人： Cornami, Inc.
CPC分类号： G06F9/3836 , G06F9/5044
摘要： A system and method to efficiently configure an array of processing cores to perform functions of a program. A function of the program is converted to a configuration of cores. The configuration is laid out in a first subset of the array of cores. The configuration is stored. The configuration is replicated to perform the function on a second subset of the array of cores.
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公开(公告)号：US20220360428A1
公开(公告)日：2022-11-10
申请号：US17860475
申请日：2022-07-08
申请人： Cornami, Inc.
摘要： Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.
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公开(公告)号：US11055103B2
公开(公告)日：2021-07-06
申请号：US16126918
申请日：2018-09-10
申请人： Cornami, Inc
发明人： Frederick Furtek , Paul Master
IPC分类号： G06F9/46 , G06F9/38 , G06F9/50 , G06F15/173 , G06F9/48
摘要： A method and system of efficient use and programming of a multi-processing core device. The system includes a programming construct that is based on stream-domain code. A programmable core based computing device is disclosed. The computing device includes a plurality of processing cores coupled to each other. A memory stores stream-domain code including a stream defining a stream destination module and a stream source module. The stream source module places data values in the stream and the stream conveys data values from the stream source module to the stream destination module. A runtime system detects when the data values are available to the stream destination module and schedules the stream destination module for execution on one of the plurality of processing cores.
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