公开(公告)号：US11960884B2

公开(公告)日：2024-04-16

申请号：US17517351

申请日：2021-11-02

申请人： Intel Corporation

发明人： Robert Valentine ,  Mark Charney ,  Raanan Sade ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal ,  Roman S. Dubtsov

IPC分类号： G06F9/30 ,  G06F7/48 ,  G06F9/38 ,  G06F17/10

CPC分类号： G06F9/3001 ,  G06F7/4812 ,  G06F9/30014 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/3016 ,  G06F7/4806 ,  G06F9/30167 ,  G06F9/382 ,  G06F9/3824 ,  G06F17/10

摘要： An embodiment of the invention is a processor including execution circuitry to calculate, in response to a decoded instruction, a result of a complex multiplication of a first complex number and a second complex number. The calculation includes a first operation to calculate a first term of a real component of the result and a first term of the imaginary component of the result. The calculation also includes a second operation to calculate a second term of the real component of the result and a second term of the imaginary component of the result. The processor also includes a decoder, a first source register, and a second source register. The decoder is to decode an instruction to generate the decoded instruction. The first source register is to provide the first complex number and the second source register is to provide the second complex number.

公开(公告)号：US09372678B2

公开(公告)日：2016-06-21

申请号：US14129438

申请日：2013-06-14

申请人： Intel Corporation

发明人： Ganesh Bikshandi ,  Daehyun Kim

IPC分类号： G06F9/45

CPC分类号： G06F8/443 ,  G06F7/4806 ,  G06F7/556 ,  G06F8/4434 ,  G06F8/452 ,  G06F17/10 ,  G06F2207/5561

摘要： Technologies for optimizing complex exponential calculations include a computing device with optimizing compiler. The compiler parses source code, optimizes the parsed representation of the source code, and generates output code. During optimization, the compiler identifies a loop in the source code including a call to the exponential function having an argument that is a loop-invariant complex number multiplied by the loop index variable. The compiler tiles the loop to generate a pair of nested loops. The compiler generates code to pre-compute the exponential function and store the resulting values in a pair of coefficient arrays. The size of each coefficient array may be equal to the square root of the number of loop iterations. The compiler applies rewrite rules to replace the exponential function call with a multiplicative expression of one element from each of the coefficient arrays. Other embodiments are described and claimed.

摘要翻译： 用于优化复数指数计算的技术包括具有优化编译器的计算设备。 编译器解析源代码，优化源代码的解析表示，并生成输出代码。 在优化期间，编译器识别源代码中的循环，包括对具有循环不变复数乘以循环索引变量的参数的指数函数的调用。 编译器平铺循环以生成一对嵌套循环。 编译器生成代码以预先计算指数函数，并将结果值存储在一对系数数组中。 每个系数数组的大小可以等于循环次数的平方根。 编译器使用重写规则来替换来自每个系数数组的一个元素的乘法表达式的指数函数调用。 描述和要求保护其他实施例。

公开(公告)号：US20120173600A1

公开(公告)日：2012-07-05

申请号：US13210455

申请日：2011-08-16

申请人： Young Hwan Park ,  Ho YANG

发明人： Young Hwan Park ,  Ho YANG

IPC分类号： G06F17/10

CPC分类号： G06F17/10 ,  G06F7/4806 ,  G06F7/4812 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/3887 ,  G06F2207/3828

摘要： Provided are an apparatus and method for performing a complex number operation using a Single Instruction Multiple Data (SIMD) architecture. A SIMD operation apparatus may perform, in parallel, a real part operation and an imaginary part operation of a plurality of complex numbers. The real part operation and the imaginary part operation may be performed sequentially, or in parallel.

摘要翻译： 提供了一种使用单指令多数据（SIMD）架构来执行复数操作的装置和方法。 SIMD操作装置可以并行地执行多个复数的实部操作和虚部操作。 可以顺序地或并行地执行实部操作和虚部操作。

公开(公告)号：US08041756B1

公开(公告)日：2011-10-18

申请号：US11856737

申请日：2007-09-18

申请人： Earle Jennings

发明人： Earle Jennings

IPC分类号： G06F1/02

CPC分类号： G06F7/57 ,  G06F1/0307 ,  G06F7/4806 ,  G06F7/5235

摘要： The invention includes apparatus and methods for high-speed calculation of non-linear functions based upon a shifted adder and a offset generator. Various implementations may preferably include a input preprocessor and/or an output post processor. The invention includes a family of core cells built from instances of these calculators providing an upward, functionally compatible, extension to a family of Application Specific Integrated Circuit (ASIC) core cells. All of these core cells consistently provide the ability to perform high speed DSP tasks including Fast Fourier Transforms (FFTs), Finite Impulse Response (FIR) filters and Infinite Impulse Response (IIR) filters. The core cells built from the calculators can concurrently perform many non-linear function calculations. The core cells can switch between tasks every clock cycle.

摘要翻译： 本发明包括用于基于移位的加法器和偏移发生器高速计算非线性函数的装置和方法。 各种实现可以优选地包括输入预处理器和/或输出后处理器。 本发明包括从这些计算器的实例构建的一系列核心单元，向专用集成电路（ASIC）核心单元系列提供向上的功能上兼容的扩展。 所有这些核心单元一直提供执行高速DSP任务的能力，包括快速傅里叶变换（FFT），有限脉冲响应（FIR）滤波器和无限脉冲响应（IIR）滤波器。 从计算器构建的核心单元可以同时执行许多非线性函数计算。 核心单元可以在每个时钟周期之间切换任务。

公开(公告)号：US20110082895A1

公开(公告)日：2011-04-07

申请号：US12877922

申请日：2010-09-08

申请人： Michael T. Everest

发明人： Michael T. Everest

IPC分类号： G06F17/10

CPC分类号： G06F7/4806

摘要： A topological categorization method, based on inclusive intervals, provides a general method of analyzing escape topologies for discrete dynamic systems, in complex and higher dimensions, including the calculation of both potential for complex and hypercomplex and field lines for complex iterations

摘要翻译： 基于包容性间隔的拓扑分类方法提供了一种在复杂和更高维度中分析离散动态系统的逃生拓扑的一般方法，包括计算复杂和超复合的潜力以及复杂迭代的场线

公开(公告)号：US07529789B2

公开(公告)日：2009-05-05

申请号：US10978778

申请日：2004-11-01

申请人： Christopher R. Hansen ,  Felician Bors ,  Terry C. Brown

发明人： Christopher R. Hansen ,  Felician Bors ,  Terry C. Brown

IPC分类号： G06F17/14

CPC分类号： G06F7/4806 ,  G06F7/483 ,  G06F17/142 ,  H04L27/2601

摘要： A method for storage for complex numbers that employs a shared exponent field is disclosed. Rather than each floating point component of an complex number having its own distinct signed mantissa and exponent fields, each component includes a distinct signed mantissa field and shares an exponent field, thereby increasing the possible size of each distinct signed mantissa field by as much as one half the number of bits formerly employed to store a single distinct exponent field.

摘要翻译： 公开了一种用于存储采用共享指数域的复数的方法。 不是每个具有其独特的有符号尾数和指数字段的复数的每个浮点分量，每个分量包括一个不同的有符号尾数字段，并且共享一个指数字段，从而将每个不同有符号尾数字段的可能大小增加多达一个 以前用于存储单个不同指数字段的位数的一半。

公开(公告)号：US20050193185A1

公开(公告)日：2005-09-01

申请号：US10956091

申请日：2004-10-04

申请人： Mark Taunton ,  Andrew Dawson

发明人： Mark Taunton ,  Andrew Dawson

IPC分类号： G06F15/00

CPC分类号： G06F9/30014 ,  G06F7/4806 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3873 ,  G06F9/3887

摘要： Methods and systems for executing SIMD instructions that efficiently implement new SIMD instructions and conventional existing SIMD MAC-type instructions, while avoiding replication of functions in order to keep the size of the logic circuit size to as low a level as can reasonably be achieved. An instruction unit executes Single Instruction Multiple Data instructions, including instructions acting on operands representing complex numbers. The instruction unit includes functional blocks that are commonly utilized to execute a plurality of the instructions, wherein the plurality of instructions utilize various individual functional blocks in various combinations with one another. The plurality of instructions is optionally executed in a pipeline fashion.

摘要翻译： 用于执行SIMD指令的方法和系统，其有效地实现新的SIMD指令和常规的现有SIMD MAC型指令，同时避免功能的复制，以便将逻辑电路尺寸的大小保持在可以合理地达到的低水平。 指令单元执行单指令多数据指令，包括作用于表示复数的操作数的指令。 指令单元包括通常用于执行多个指令的功能块，其中多个指令利用彼此各种组合的各种各样的功能块。 多个指令可选地以流水线方式执行。

公开(公告)号：US20040010436A1

公开(公告)日：2004-01-15

申请号：US10607708

申请日：2003-06-27

发明人： Carol Fields

IPC分类号： G06F017/60

CPC分类号： G06Q30/08 ,  G06F1/0307 ,  G06F7/4806 ,  G06F7/5235 ,  G06F7/57 ,  G06Q30/02

摘要： The invention provides a method and a mechanism for a terminal service organization enlisting a customer for a web-service, including the following. The terminal service organization provides an avenue referring which the customer to the web-service. The customer uses the avenue to engage the web-service to provide at least one web-service product creating a web-site revenue for the web-service. The web-site product is customized by at least one instruction from the customer. And the terminal service organization receives an organization revenue based upon the customer using the avenue to create the web-site revenue. The terminal service organization benefits by receiving the organization revenue from the use of the avenue by the customer. The customer benefits in being able to use the avenue to instruct the web-service to create the web-service products. These web-service products include at least one web-site component. Each web-site component is an instance of a web-site component collection.

摘要翻译： 本发明提供了一种终端服务组织招募用户的Web服务的方法和机制，包括以下内容。 终端服务机构为客户提供一个通向网络服务的通道。 客户使用该渠道来使网络服务提供至少一个Web服务产品，为网络服务创建网站收入。 网站产品由客户至少提供一条指令定制。 终端服务机构根据客户使用该渠道收取组织收入，创建网站收入。 终端服务组织通过接收客户使用该路径的组织收入来获益。 客户可以利用这些渠道来指导网络服务来创建网络服务产品。 这些网络服务产品至少包括一个网站组件。 每个网站组件都是网站组件集合的实例。

公开(公告)号：US20030154226A1

公开(公告)日：2003-08-14

申请号：US10189195

申请日：2002-07-05

发明人： Solomon Khmelnik

IPC分类号： G06F007/38

CPC分类号： G06F7/4806 ,  G06F7/49

摘要： The invention provides a method and apparatus for storing complex number data in formats or codes which allow efficient complex number arithmetic operations to be performed and for performing such complex number arithmetic operations. According to one aspect of the invention, a method for coding complex numbers is provided for use in a data processing system. In response to receiving an instruction, two data elements representing the real and imaginary parts of a complex number are read. These two elements are then used to generate a single code for the complex number which is stored as a single data element. As a result of this coding, arithmetic operations on complex numbers may be performed on a single data element which contains both real and imaginary data. According to another aspect of the invention, a coprocessor is described. This coprocessor has stored therein data representing sequences of instructions which, when combined with certain unique circuitry also contained therein and executed, cause the coprocessor to perform the above described method and to perform complex number arithmetic operations.

摘要翻译： 本发明提供一种用于存储允许执行有效复数算术运算并执行这种复数算术运算的格式或代码中的复数数据的方法和装置。 根据本发明的一个方面，提供一种用于编码复数的方法，用于数据处理系统。 响应于接收到指令，读取表示复数的实部和虚部的两个数据元素。 然后，这两个元素用于为存储为单个数据元素的复数生成单个代码。 作为该编码的结果，可以对包含实数数据和虚数据的单个数据元素执行关于复数的算术运算。 根据本发明的另一方面，描述了协处理器。 该协处理器在其中存储了表示指令序列的数据，当与其中还包含并执行的某些唯一电路组合时，使得协处理器执行上述方法并执行复数算术运算。

公开(公告)号：US20020169812A1

公开(公告)日：2002-11-14

申请号：US09823928

申请日：2001-03-31

发明人： John T. Orchard

IPC分类号： G06F007/52 ,  G06F007/50

CPC分类号： G06F7/5443 ,  G06F7/4806

摘要： A method is presented comprising analyzing two or more input terms on a per-bit basis within each level of bit-significance. Maximally segmenting each of the levels of bit-significance into one or more one-, two-, and/or three-bit groups, and designing a hyperpipelined hybrid Wallace tree adder utilizing one or more full-adders, half-adders, and associated register based, at least in part, on the maximal segmentation of the input terms.

摘要翻译： 提出了一种方法，其包括在每一比特重要级别内以每比特为基础分析两个或多个输入项。 将比特重要级别中的每一个最大程度地分割成一个或多个一个，两个和/或三个比特组，并且使用一个或多个全加法器，加法器和相关联的设计超线程混合华莱士树加法器 至少部分地基于输入项的最大分割。