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公开(公告)号：US07286572B2
公开(公告)日：2007-10-23
申请号：US10338972
申请日：2003-01-10
IPC分类号： H04J3/02
CPC分类号： H04J3/0685 , H04J3/047 , Y10S370/907
摘要： An integrated circuit includes a serdes framer interface (SFI) circuit for receiving a first set of data channels and a reference channel, generating first logic levels for the first set of data channels, and realigning the first set of data channels relative to a reference channel. The integrated circuit further includes a multiplexing circuit for receiving a second set of data channels and for merging the second set of data channels into one or more data channels. The second set of data channels is generated based on the first set of data channels. A data rate of the one or more data channels is higher than a data rate of the second set of data channels.
摘要翻译： 集成电路包括用于接收第一组数据信道和参考信道的serdes成帧器接口（SFI）电路，为第一组数据信道生成第一逻辑电平，并相对于参考信道重新对准第一组数据信道 。 集成电路还包括多路复用电路，用于接收第二组数据信道并将第二组数据信道合并成一个或多个数据信道。 基于第一组数据信道生成第二组数据信道。 一个或多个数据信道的数据速率高于第二组数据信道的数据速率。
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公开(公告)号：US07848367B2
公开(公告)日：2010-12-07
申请号：US11896162
申请日：2007-08-30
IPC分类号： H04J3/02
CPC分类号： H04J3/0685 , H04J3/047 , Y10S370/907
摘要： High-speed, high-performance, low-power transponders, serializers and deserializers are disclosed. A serializer may include a serdes framer interface (SFI) circuit, a clock multiplier unit, and a multiplexing circuit. A deserializer may include an input receiver circuit for receiving and adjusting an input data signal, a clock and data recovery circuit (CDR) for recovering clock and data signals, a demultiplexing circuit for splitting one or more data channels into a higher number of data channels, and a serdes framer interface (SFI) circuit for generating a reference channel and generating output data channels to be sent to a framer. The input receiver circuit may include a limiting amplifier. Each of the serializer and deserializer may further include a pseudo random pattern generator and error checker unit. The serializer and deserializer each may be integrated into its respective semiconductor chip or both may be integrated into a single semiconductor chip.
摘要翻译： 公开了高速，高性能，低功率转发器，串行器和解串器。 串行器可以包括serdes成帧器接口（SFI）电路，时钟乘法器单元和复用电路。 解串器可以包括用于接收和调整输入数据信号的输入接收器电路，用于恢复时钟和数据信号的时钟和数据恢复电路（CDR），用于将一个或多个数据信道分成更多数量的数据信道的解复用电路 以及用于产生参考信道并产生要发送到成帧器的输出数据信道的Serdes成帧器接口（SFI）电路。 输入接收机电路可以包括限幅放大器。 串行器和解串器中的每一个还可以包括伪随机模式发生器和错误检查器单元。 串行器和解串器各自可以集成到其相应的半导体芯片中，或者两者可以集成到单个半导体芯片中。
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3.发明申请Encoding and decoding architecture and method for pipelining encoded data or pipelining with a look-ahead strategy 有权编码和解码结构和方法，用于流水线编码数据或流水线与预先策略公开(公告)号：US20080118246A1
公开(公告)日：2008-05-22
申请号：US11641363
申请日：2006-12-18
申请人： Samuel A. Steidl , Peter F. Curran
发明人： Samuel A. Steidl , Peter F. Curran
CPC分类号： H04L27/2075
摘要： An encoding and/or decoding communication system comprises a framer interface, an encoder, a multiplexer, an output driver, and a clock multiplier unit (CMU). The encoder includes an input latch circuitry stage; an output latch circuitry stage; an intermediate latch circuitry stage interposed between the input latch circuitry stage and the output latch circuitry stage, the intermediate latch circuitry stage coupled to the input latch circuitry stage and the output latch circuitry stage; a plurality of encoding logic circuitry stages interposed between the input latch circuitry stage and the output latch circuitry stage, a last one of the plurality of encoding logic circuitry stages placed adjacent to the output latch circuitry stage and coupled to the output latch circuitry stage; and a feedback between the output latch circuitry stage and the last one of the plurality of encoding logic circuitry stages.
摘要翻译： 编码和/或解码通信系统包括成帧器接口，编码器，多路复用器，输出驱动器和时钟倍增器单元（CMU）。 编码器包括输入锁存电路级; 输出锁存电路级; 插入在输入锁存电路级和输出锁存电路级之间的中间锁存电路级，中间锁存电路级耦合到输入锁存电路级和输出锁存电路级; 插入在输入锁存电路级和输出锁存电路级之间的多个编码逻辑电路级，多个编码逻辑电路级中的最后一个与输出锁存电路级放置并耦合到输出锁存电路级; 以及输出锁存电路级与多个编码逻辑电路级中的最后一个之间的反馈。
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4.发明授权Encoding and decoding architecture and method for pipelining encoded data or pipelining with a look-ahead strategy 有权编码和解码结构和方法，用于流水线编码数据或流水线与预先策略公开(公告)号：US07933354B2
公开(公告)日：2011-04-26
申请号：US11641363
申请日：2006-12-18
申请人： Samuel A. Steidl , Peter F. Curran
发明人： Samuel A. Steidl , Peter F. Curran
IPC分类号： H04L27/10
CPC分类号： H04L27/2075
摘要： An encoding and/or decoding communication system comprises a framer interface, an encoder, a multiplexer, an output driver, and a clock multiplier unit (CMU). The encoder includes an input latch circuitry stage; an output latch circuitry stage; an intermediate latch circuitry stage interposed between the input latch circuitry stage and the output latch circuitry stage, the intermediate latch circuitry stage coupled to the input latch circuitry stage and the output latch circuitry stage; a plurality of encoding logic circuitry stages interposed between the input latch circuitry stage and the output latch circuitry stage, a last one of the plurality of encoding logic circuitry stages placed adjacent to the output latch circuitry stage and coupled to the output latch circuitry stage; and a feedback between the output latch circuitry stage and the last one of the plurality of encoding logic circuitry stages.
摘要翻译： 编码和/或解码通信系统包括成帧器接口，编码器，多路复用器，输出驱动器和时钟倍增器单元（CMU）。 编码器包括输入锁存电路级; 输出锁存电路级; 插入在输入锁存电路级和输出锁存电路级之间的中间锁存电路级，中间锁存电路级耦合到输入锁存电路级和输出锁存电路级; 插入在输入锁存电路级和输出锁存电路级之间的多个编码逻辑电路级，多个编码逻辑电路级中的最后一个与输出锁存电路级放置并耦合到输出锁存电路级; 以及输出锁存电路级与多个编码逻辑电路级中的最后一个之间的反馈。
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