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1.发明申请AVOIDING BIST AND MBIST INTRUSION LOGIC IN CRITICAL TIMING PATHS 有权在关键时间表中避免BIST和MBIST INTRUSION LOGIC公开(公告)号：US20120124435A1
公开(公告)日：2012-05-17
申请号：US12948702
申请日：2010-11-17
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G06F11/27 , G01R31/318536
摘要： Methods, systems, and apparatuses are presented that remove BIST intrusion logic from critical timing paths of a microcircuit design without significant impact on testing. In one embodiment, BIST data is multiplexed with scan test data and serially clocked in through scan test cells for BIST testing. In another embodiment, BIST data is injected into the feedback path of one or more data latches. In a third embodiment, BIST data is injected into the result data path of a multi-cycle ALU within an execution unit. In each embodiment, BIST circuitry is eliminated from critical timing paths.
摘要翻译： 提出了从微型电路设计的关键定时路径中去除BIST入侵逻辑的方法，系统和装置，而不会对测试产生重大影响。 在一个实施例中，BIST数据与扫描测试数据多路复用，并通过用于BIST测试的扫描测试单元串行计时。 在另一个实施例中，将BIST数据注入到一个或多个数据锁存器的反馈路径中。 在第三实施例中，将BIST数据注入执行单元内的多周期ALU的结果数据路径。 在每个实施例中，BIST电路从关键定时路径中消除。
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2.发明授权公开(公告)号：US08990623B2
公开(公告)日：2015-03-24
申请号：US12948702
申请日：2010-11-17
IPC分类号： G06F11/27 , G01R31/3185
CPC分类号： G06F11/27 , G01R31/318536
摘要： Methods, systems, and apparatuses are presented that remove BIST intrusion logic from critical timing paths of a microcircuit design without significant impact on testing. In one embodiment, BIST data is multiplexed with scan test data and serially clocked in through scan test cells for BIST testing. In another embodiment, BIST data is injected into the feedback path of one or more data latches. In a third embodiment, BIST data is injected into the result data path of a multi-cycle ALU within an execution unit. In each embodiment, BIST circuitry is eliminated from critical timing paths.
摘要翻译： 提出了从微型电路设计的关键定时路径中去除BIST入侵逻辑的方法，系统和装置，而不会对测试产生重大影响。 在一个实施例中，BIST数据与扫描测试数据多路复用，并通过用于BIST测试的扫描测试单元串行计时。 在另一个实施例中，将BIST数据注入到一个或多个数据锁存器的反馈路径中。 在第三实施例中，将BIST数据注入执行单元内的多周期ALU的结果数据路径。 在每个实施例中，BIST电路从关键定时路径中消除。
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3.发明申请公开(公告)号：US20120291037A1
公开(公告)日：2012-11-15
申请号：US13107420
申请日：2011-05-13
IPC分类号： G06F9/46
CPC分类号： G06F9/3873 , G06F9/3012 , G06F9/3836 , G06F9/3855 , G06F9/3889
摘要： A method and processor are described for implementing programmable priority encoding to track relative age order of operations in a scheduler queue. The processor may comprise a scheduler queue configured to maintain an ancestry table including a plurality of consecutively numbered row entries and a plurality of consecutively numbered columns. Each row entry includes one bit in each of the columns. Pickers are configured to pick an operation that is ready for execution based on the age of the operation as designated by the ancestry table. The column number of each bit having a select logic value indicates an operation that is older than the operation associated with the number of the row entry that the bit resides in.
摘要翻译： 描述了一种用于实现可编程优先级编码以跟踪调度器队列中的操作的相对年龄顺序的方法和处理器。 处理器可以包括调度器队列，其被配置为维护包括多个连续编号的行条目和多个连续编号的列的祖先表。 每行条目在每列中包含一位。 选择器被配置为根据由祖先表指定的操作年龄来选择准备执行的操作。 具有选择逻辑值的每个位的列号指示比该位所在的行条目的数量更早的操作。
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4.发明授权公开(公告)号：US08656401B2
公开(公告)日：2014-02-18
申请号：US13107420
申请日：2011-05-13
IPC分类号： G06F9/46
CPC分类号： G06F9/3873 , G06F9/3012 , G06F9/3836 , G06F9/3855 , G06F9/3889
摘要： A method and processor are described for implementing programmable priority encoding to track relative age order of operations in a scheduler queue. The processor may comprise a scheduler queue configured to maintain an ancestry table including a plurality of consecutively numbered row entries and a plurality of consecutively numbered columns. Each row entry includes one bit in each of the columns. Pickers are configured to pick an operation that is ready for execution based on the age of the operation as designated by the ancestry table. The column number of each bit having a select logic value indicates an operation that is older than the operation associated with the number of the row entry that the bit resides in.
摘要翻译： 描述了一种用于实现可编程优先级编码以跟踪调度器队列中的操作的相对年龄顺序的方法和处理器。 处理器可以包括调度器队列，其被配置为维护包括多个连续编号的行条目和多个连续编号的列的祖先表。 每行条目在每列中包含一位。 选择器被配置为根据由祖先表指定的操作年龄来选择准备执行的操作。 具有选择逻辑值的每个位的列号指示比该位所在的行条目的数量更早的操作。
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公开(公告)号：US20120110256A1
公开(公告)日：2012-05-03
申请号：US12914538
申请日：2010-10-28
申请人： Ganesh Venkataramanan , Kyle S. Viau , James Vinh
发明人： Ganesh Venkataramanan , Kyle S. Viau , James Vinh
CPC分类号： G11C15/04
摘要： Content-Addressable Memory (CAM) arrays and related circuitry for integrated circuits and CAM array comparison methods are provided such that relatively low power is used in the operation of the CAM circuitry. A binary value pair is stored in a pair of CAM memory elements. A comparison signal is provided to comparator circuitry that uniquely represents the stored binary values. A match signal is input to the comparator circuitry that uniquely represents a binary value pair to be compared with the stored binary value pair. In one example, a transistor is operated to output a positive match result signal only on a condition that the comparison signal provided to the comparator circuitry and match signal input to the comparator circuitry represent the same binary value pair. In that example, no transistor of the comparator circuitry is operated when the comparison signal provided to the comparator circuitry and match signal input to the comparator circuitry represent different binary value pairs.
摘要翻译： 提供用于集成电路和CAM阵列比较方法的内容寻址存储器（CAM）阵列和相关电路，使得在CAM电路的操作中使用相对较低的功率。 二进制值对存储在一对CAM存储器元件中。 将比较信号提供给唯一地表示存储的二进制值的比较器电路。 匹配信号被输入到比较器电路，其唯一地表示要与存储的二进制值对进行比较的二进制值对。 在一个示例中，晶体管被操作以仅在提供给比较器电路的比较信号和输入到比较器电路的匹配信号表示相同的二进制值对的条件下输出正匹配结果信号。 在该示例中，当提供给比较器电路的比较信号和输入到比较器电路的匹配信号表示不同的二进制值对时，不操作比较器电路的晶体管。
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6.发明授权Method and apparatus for fast decoding and enhancing execution speed of an instruction 有权用于快速解码并提高指令执行速度的方法和装置公开(公告)号：US09176738B2
公开(公告)日：2015-11-03
申请号：US13005215
申请日：2011-01-12
申请人： Ganesh Venkataramanan , Emil Talpes
发明人： Ganesh Venkataramanan , Emil Talpes
CPC分类号： G06F9/3017 , G06F9/30145 , G06F9/3836 , G06F9/3889
摘要： Method and apparatus for fast decoding of microinstructions are disclosed. An integrated circuit is disclosed wherein microinstructions are queued for execution in an execution unit having multiple pipelines where each pipeline is configured to execute a set of supported microinstructions. The execution unit receives microinstruction data including an operation code (opcode) or a complex opcode. The execution unit executes the microinstruction multiple times wherein the microinstruction is executed at least once to get an address value and at least once to get a result of an operation. The execution unit processes complex opcodes by utilizing both a load/store support and a simple opcode support by splitting the complex opcode into load/store and simple opcode components and creating an internal source/destination between the two components.
摘要翻译： 公开了用于微指令快速解码的方法和装置。 公开了一种集成电路，其中微指令被排队以在具有多个管线的执行单元中执行，其中每个管道被配置为执行一组支持的微指令。 执行单元接收包括操作码（opcode）或复合操作码的微指令数据。 执行单元多次执行微指令，其中执行微指令至少一次以获得地址值，并且至少一次以获得操作的结果。 执行单元通过将复杂操作码分解为加载/存储和简单的操作码组件并在两个组件之间创建内部源/目标位置，通过利用加载/存储支持和简单的操作码支持来处理复杂的操作码。
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7.发明申请公开(公告)号：US20120179895A1
公开(公告)日：2012-07-12
申请号：US13005215
申请日：2011-01-12
申请人： Ganesh Venkataramanan , Emil Talpes
发明人： Ganesh Venkataramanan , Emil Talpes
IPC分类号： G06F9/38
CPC分类号： G06F9/3017 , G06F9/30145 , G06F9/3836 , G06F9/3889
摘要： Method and apparatus for fast decoding of microinstructions are disclosed. An integrated circuit is disclosed wherein microinstructions are queued for execution in an execution unit having multiple pipelines where each pipeline is configured to execute a set of supported microinstructions. The execution unit receives microinstruction data including an operation code (opcode) or a complex opcode. The execution unit executes the microinstruction multiple times wherein the microinstruction is executed at least once to get an address value and at least once to get a result of an operation. The execution unit processes complex opcodes by utilizing both a load/store support and a simple opcode support by splitting the complex opcode into load/store and simple opcode components and creating an internal source/destination between the two components.
摘要翻译： 公开了用于微指令快速解码的方法和装置。 公开了一种集成电路，其中微指令被排队以在具有多个管线的执行单元中执行，其中每个管道被配置为执行一组支持的微指令。 执行单元接收包括操作码（opcode）或复合操作码的微指令数据。 执行单元多次执行微指令，其中执行微指令至少一次以获得地址值，并且至少一次以获得操作的结果。 执行单元通过将复杂操作码分解为加载/存储和简单的操作码组件并在两个组件之间创建内部源/目标位置，通过利用加载/存储支持和简单的操作码支持来处理复杂的操作码。
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8.发明申请METHOD AND APPARATUS FOR PERFORMING A MEMORY BUILT-IN SELF-TEST ON A PLURALITY OF MEMORY ELEMENT ARRAYS 审中-公开用于对大量存储元件阵列进行内存建立自检的方法和装置公开(公告)号：US20120137185A1
公开(公告)日：2012-05-31
申请号：US12956688
申请日：2010-11-30
申请人： Ganesh Venkataramanan , Wei-Yu Chen
发明人： Ganesh Venkataramanan , Wei-Yu Chen
CPC分类号： G11C29/26
摘要： A method and apparatus are described for performing a memory built-in self-test (MBIST) on a plurality of memory element arrays. Control packets are output over a first ring bus to respective ones of the arrays. Each of the arrays receives its respective control packet via the first ring bus, and reads commands residing in a plurality of fields within the respective control packet. Each of the arrays performs at least one self-test based on the commands, and outputs a respective result packet over a second ring bus. Each result packet indicates the results of the self-test performed on the array. Each control packet is transmitted in its own individual time slot to a respective one of the arrays.
摘要翻译： 描述了用于在多个存储元件阵列上执行存储器内置自检（MBIST）的方法和装置。 控制分组通过第一环形总线输出到阵列中的相应阵列。 每个阵列经由第一环形总线接收其相应的控制分组，并且读取驻留在相应控制分组内的多个字段中的命令。 每个阵列基于命令执行至少一个自检，并且通过第二环形总线输出相应的结果分组。 每个结果包指示在阵列上执行的自检的结果。 每个控制分组在其各自的时隙中发送到阵列中的相应的一个阵列。
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9.发明申请公开(公告)号：US20140025933A1
公开(公告)日：2014-01-23
申请号：US13550875
申请日：2012-07-17
IPC分类号： G06F9/30
CPC分类号： G06F9/3832 , G06F9/3824 , G06F9/3836 , G06F9/3861
摘要： A method for reducing a number of operations replayed in a processor includes decoding an operation to determine a memory address and a command in the operation. If data is not in a way predictor based on the memory address, a suppress wakeup signal is sent to an operation scheduler, and the operation scheduler suppresses waking up other operations that are dependent on the data.
摘要翻译： 一种用于减少在处理器中重放的操作数量的方法包括解码操作以确定操作中的存储器地址和命令。 如果数据不是基于存储器地址的预测器，则将抑制唤醒信号发送到操作调度器，并且操作调度器抑制唤醒依赖于数据的其他操作。
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公开(公告)号：US20120144393A1
公开(公告)日：2012-06-07
申请号：US12957861
申请日：2010-12-01
IPC分类号： G06F9/46
CPC分类号： G06F9/3836 , G06F9/3855
摘要： A method and apparatus for scheduling execution of instructions in a multi-issue processor. The apparatus includes post wake logic circuitry configured to track a plurality of entries corresponding to a plurality of instructions to be scheduled. Each instruction has at least one associated source address and a destination address. The post wake logic circuitry is configured to drive a ready input indicating an entry that is ready for execution based on a current match input. A picker circuitry is configured to pick an instruction for execution based the ready input. A compare circuit is configured to determine the destination address for the picked instruction, compare the destination address to the source address for all entries and drive the current match input.
摘要翻译： 一种用于调度多问题处理器中的指令执行的方法和装置。 该装置包括配置为跟踪与要调度的多个指令相对应的多个条目的后唤醒逻辑电路。 每个指令至少有一个关联的源地址和目标地址。 后唤醒逻辑电路被配置为基于当前匹配输入来驱动指示准备执行的条目的就绪输入。 拾取器电路被配置为基于准备输入来选择用于执行的指令。 比较电路被配置为确定拾取的指令的目标地址，将目的地址与所有条目的源地址进行比较，并驱动当前匹配输入。
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