公开(公告)号：US11861374B2

公开(公告)日：2024-01-02

申请号：US18063984

申请日：2022-12-09

Applicant: Cryptography Research, Inc.

Inventor： Ashish Raj ,  Joel Wittenauer ,  Winthrop John Wu ,  Qinglai Xiao ,  Samatha Gummalla ,  Bryan Jason Wang

IPC: G06F9/445

CPC classification number: G06F9/445

Abstract: A computing system includes a host device and a root of trust (RoT) device for performing batch encryption and decryption operations facilitated by a direct memory access (DMA) engine. The host device generates a command table for batch processing of a set of address tables that each describe a set of data blocks of a file to be encrypted or decrypted. The DMA engine facilitates a DMA transfer of the command table from the host memory to an RoT memory of the RoT device. The RoT device then performs batch processing of the address tables referenced in the command table. For each address table, the DMA engine copies a set of data blocks from the host memory to the RoT memory, a cryptographic engine encrypts or decrypts the data blocks, and the DMA engine copies the transformed data blocks back to the host memory.

公开(公告)号：US20230195553A1

公开(公告)日：2023-06-22

申请号：US18077943

申请日：2022-12-08

Applicant: Cryptography Research, Inc.

Inventor： Bryan Jason Wang ,  Samatha Gummalla

IPC: G06F11/07

CPC classification number: G06F11/0781 ,  G06F11/073 ,  G06F11/0793

Abstract: Technologies for detecting and classifying errors detected in pipelined hardware are described. One device includes a hardware pipeline with a set of pipeline stages. Error detection logic can detect an error in the hardware pipeline, and control logic can classify the error in one of the multiple categories based on a type of the error, a position of the first data in a data stream that triggered the error, and a position of a pipeline stage in which the error is detected. The control logic can perform an error-response action based on the error classification of the error.

公开(公告)号：US20230185745A1

公开(公告)日：2023-06-15

申请号：US18063959

申请日：2022-12-09

Applicant: Cryptography Research, Inc.

Inventor： Winthrop John Wu ,  Samatha Gummalla ,  Bryan Jason Wang

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: A DMA system includes two or more DMA engines that facilitate transfers of data through a shared memory. The DMA engines may operate independently of each other and with different throughputs. A data flow control module controls data flow through the shared memory by tracking status information of data blocks in the shared memory. The data flow control module updates the status information in response to read and write operations to indicate whether each block includes valid data that has not yet been read or if the block has been read and is available for writing. The data flow control module shares the status information with the DMA engines via a side-channel interface to enable the DMA engines to determine which block to write to or read from.

公开(公告)号：US12229065B2

公开(公告)日：2025-02-18

申请号：US18063959

申请日：2022-12-09

Applicant: Cryptography Research, Inc.

Inventor： Winthrop John Wu ,  Samatha Gummalla ,  Bryan Jason Wang

IPC: G06F13/28

Abstract: A DMA system includes two or more DMA engines that facilitate transfers of data through a shared memory. The DMA engines may operate independently of each other and with different throughputs. A data flow control module controls data flow through the shared memory by tracking status information of data blocks in the shared memory. The data flow control module updates the status information in response to read and write operations to indicate whether each block includes valid data that has not yet been read or if the block has been read and is available for writing. The data flow control module shares the status information with the DMA engines via a side-channel interface to enable the DMA engines to determine which block to write to or read from.

公开(公告)号：US12131067B2

公开(公告)日：2024-10-29

申请号：US17987092

申请日：2022-11-15

Applicant: Cryptography Research, Inc.

Inventor： Thomas J. Thatcher ,  Bryan Jason Wang

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0673

Abstract: Multiple (e.g., two) hosts access a single memory channel (and/or device) via a memory controller. The single memory channel/device can support at most one access at a time. To reduce contention between the multiple hosts, the memory controller comprises multiple (e.g., two), independent, host ports. Each host port is associated with a write buffer(s) in the memory controller that stores write data at least until the memory controller writes the data to the memory channel. Data stored in a write buffer may be used to respond to memory access commands (e.g., reads or writes) on the ports without accessing the memory channel. In this manner, the hosts do not directly contend with each other for the single memory channel or the memory controller.

公开(公告)号：US20230195477A1

公开(公告)日：2023-06-22

申请号：US18063984

申请日：2022-12-09

Applicant: Cryptography Research, Inc.

Inventor： Ashish Raj ,  Joel Wittenauer ,  Winthrop John Wu ,  Qinglai Xiao ,  Samatha Gummalla ,  Bryan Jason Wang

IPC: G06F9/445

CPC classification number: G06F9/445

Abstract: A computing system includes a host device and a root of trust (RoT) device for performing batch encryption and decryption operations facilitated by a direct memory access (DMA) engine. The host device generates a command table for batch processing of a set of address tables that each describe a set of data blocks of a file to be encrypted or decrypted. The DMA engine facilitates a DMA transfer of the command table from the host memory to an RoT memory of the RoT device. The RoT device then performs batch processing of the address tables referenced in the command table. For each address table, the DMA engine copies a set of data blocks from the host memory to the RoT memory, a cryptographic engine encrypts or decrypts the data blocks, and the DMA engine copies the transformed data blocks back to the host memory.