公开(公告)号：US20230239936A1

公开(公告)日：2023-07-27

申请号：US17581814

申请日：2022-01-21

申请人： DAVID TODD MILLER

发明人： DAVID TODD MILLER

IPC分类号： H04W74/08 ,  H04B1/00 ,  H04W28/08

CPC分类号： H04W74/0891 ,  H04W74/0875 ,  H04B1/0003 ,  H04W28/0983 ,  H04L27/2655

摘要： A typical Software Defined Radio (SDR) receiver for Binary Phase Shift Keying (BPSK) or higher order modulations accepts an incoming digital serial complex I/O channel sample stream and performs demodulation functions to recover the original baseband data stream that another source transmitted. Typically, for real-time high data rate (HDR)>5.0 Megabits per second (Mbps) operations, a SDR unit requires an Application Specific Integrated Circuit (ASIC) component or Field Programmable Gate Array (FPGA) component to perform the customized Digital Signal Processing (DSP) intensive processing functions in real-time. However, ASIC chips and FPGAs are typically relatively expensive to develop, purchase, and/or reconfigure. With the parallel multi-core algorithm method of this claim, one can now implement a real-time HDR (>5.0 Mbps) SDR Demodulator with only Commercial-Off-The-Shelf (COTS) software, a relatively inexpensive personal computer (PC) or server that contains a single multi-core General Purpose Processor (GPP), and especially without using ASICS or FPGAs.