METHODS AND SYSTEMS FOR ADJUSTING NETWORK SPEED TO A GATEWAY

    公开(公告)号:US20240015596A1

    公开(公告)日:2024-01-11

    申请号:US17862064

    申请日:2022-07-11

    IPC分类号: H04W28/20 H04W28/12 H04W28/08

    摘要: The present disclosure is directed to methods and systems for adjusting network speed to a gateway. The network speed adjustment system can include a gateway with the ability to manage a consumer-initiated temporary increase in network speed or network bandwidth. The network speed adjustment system can determine whether the provisioning system can support a network speed increase to the gateway. The provisioning system can measure the capacity of the network at the gateway location and determine whether the system can support providing the gateway with an increased network speed or increased bandwidth. When additional bandwidth capacity or network speed is available for a gateway location, a user can request the network increase by submitting a token via the gateway. The gateway can communicate with the provisioning system to increase the network speed according to the characteristics of the token.

    REAL-TIME HIGH DATA RATE DEMODULATION METHOD USING MULTI-CORES OF GENERAL PURPOSE PROCESSOR IN PARALLEL

    公开(公告)号:US20230239936A1

    公开(公告)日:2023-07-27

    申请号:US17581814

    申请日:2022-01-21

    申请人: DAVID TODD MILLER

    发明人: DAVID TODD MILLER

    IPC分类号: H04W74/08 H04B1/00 H04W28/08

    摘要: A typical Software Defined Radio (SDR) receiver for Binary Phase Shift Keying (BPSK) or higher order modulations accepts an incoming digital serial complex I/O channel sample stream and performs demodulation functions to recover the original baseband data stream that another source transmitted. Typically, for real-time high data rate (HDR)>5.0 Megabits per second (Mbps) operations, a SDR unit requires an Application Specific Integrated Circuit (ASIC) component or Field Programmable Gate Array (FPGA) component to perform the customized Digital Signal Processing (DSP) intensive processing functions in real-time. However, ASIC chips and FPGAs are typically relatively expensive to develop, purchase, and/or reconfigure. With the parallel multi-core algorithm method of this claim, one can now implement a real-time HDR (>5.0 Mbps) SDR Demodulator with only Commercial-Off-The-Shelf (COTS) software, a relatively inexpensive personal computer (PC) or server that contains a single multi-core General Purpose Processor (GPP), and especially without using ASICS or FPGAs.

    Method and system for controlling the use of dormant capacity for distributing data

    公开(公告)号:US11997527B2

    公开(公告)日:2024-05-28

    申请号:US17353989

    申请日:2021-06-22

    申请人: Siden, Inc.

    IPC分类号: H04W28/02 H04H20/42 H04W28/08

    摘要: A method and system for controlling the use of dormant capacity for distributing data includes communicating data as part of a regular traffic load through a network having an overall network capacity, determining a dormant capacity of the network based on regular network traffic load, delivering content to a plurality of devices through the network, receiving the data at the plurality of devices, based on receiving the data, measuring an efficiency metric at each of the plurality of devices, communicating the efficiency metric of the devices to a service provider, receiving the efficiency metric at the service provider from the devices, receiving a resource usage report from the network, determining a target throughput for each of the plurality of devices based on the resource usage report and communicating second data to the plurality of devices from a content delivery service based on the target throughput using the dormant capacity.