公开(公告)号：US20210151385A1

公开(公告)日：2021-05-20

申请号：US17159610

申请日：2021-01-27

Applicant: DENSO CORPORATION

Inventor： Aiko KAJI ,  Haruhito ICHIKAWA ,  Shuhei MITANI ,  Tomohiro MIMURA ,  Yukihiro WAKASUGI ,  Narumasa SOEJIMA

IPC: H01L23/544 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/45 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device includes: forming an insulating film on a surface of a semiconductor layer of a semiconductor substrate; forming a contact hole in the insulating film; forming a conductor material on the insulating film to be in contact with the semiconductor layer through the contact hole; and patterning the conductor material using an alignment key included in the conductor material.

公开(公告)号：US20200243404A1

公开(公告)日：2020-07-30

申请号：US16750286

申请日：2020-01-23

Applicant: DENSO CORPORATION

Inventor： Aiko KAJI ,  Yoshiaki YAMANOUCHI ,  Jun SAITO

IPC: H01L21/66 ,  H01L21/3065

Abstract: A manufacturing method of a semiconductor device includes: forming a second conductive type layer over a first conductive type layer; and forming a trench by etching the second conductivity type layer by a plasma etching process to expose the first conductivity type layer. The etching of the second conductivity type layer includes: performing a spectroscopic analysis of light emission of plasma; detecting an interface between the first conductivity type layer and the second conductivity type layer based on a change in emission intensity; and stopping the etching of the second conductivity type layer when an end point is determined based on a detection result of the interface.

公开(公告)号：US20200168732A1

公开(公告)日：2020-05-28

申请号：US16776821

申请日：2020-01-30

Applicant: DENSO CORPORATION

Inventor： Shuhei MITANI ,  Aiko KAJI ,  Yasuhiro EBIHARA ,  Tatsuji NAGAOKA ,  Sachiko AOI

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66

Abstract: A silicon carbide semiconductor device includes: a substrate; a first impurity region on the substrate; a base region on the first impurity region; a second impurity region in the base region; a trench gate structure including a gate insulation film and a gate electrode in a trench; a first electrode connected to the second impurity region and the base region; a second electrode on a rear surface of the substrate; a first current dispersion layer between the first impurity region and the base region; a plurality of first deep layers in the second current dispersion layer; a second current dispersion layer between the first current dispersion layer and the base region; and a second deep layer between the first current dispersion layer and the base region apart from the trench.