公开(公告)号：US09094037B2

公开(公告)日：2015-07-28

申请号：US13331923

申请日：2011-12-20

申请人： Daijiro Harada ,  Takashi Utsumi

发明人： Daijiro Harada ,  Takashi Utsumi

IPC分类号： G06F3/00 ,  H03M1/12

CPC分类号： G06F13/102 ,  G06F13/4221 ,  H03M1/00 ,  H03M1/12 ,  H03M1/122

摘要： There is a need to cause a delay to occur less frequently than the related art during processing of an input signal in need of relatively fast processing. In a semiconductor device, a conversion portion includes first channels and second channels and A/D converts a signal input to a selected channel. A signal input to the first channel requires faster processing than a signal input to the second channel. The conversion portion receives a scan conversion instruction from a central processing unit, sequentially selects the input channels in a specified selection order, and successively performs A/D conversion. In this case, the conversion portion notifies a peripheral circuit of completion of A/D conversion after completion of A/D conversion on signals input to the first channels and before completion of A/D conversion on input signals input to all input channels.

摘要翻译： 在需要相对较快处理的输入信号的处理期间，需要在现有技术中引起比较少频率的延迟。 在半导体器件中，转换部分包括第一通道和第二通道，并且A / D转换输入到所选通道的信号。 输入到第一通道的信号需要比输入到第二通道的信号更快的处理。 转换部分从中央处理单元接收扫描转换指令，按指定的选择顺序依次选择输入通道，并依次进行A / D转换。 在这种情况下，转换部分在对输入到第一通道的信号和在输入到所有输入通道的输入信号上完成A / D转换之后的A / D转换完成之后通知外围电路完成A / D转换。

公开(公告)号：US5826059A

公开(公告)日：1998-10-20

申请号：US574142

申请日：1995-12-18

申请人： Daijiro Harada ,  Katsunobu Hongo ,  Masato Koura

发明人： Daijiro Harada ,  Katsunobu Hongo ,  Masato Koura

IPC分类号： G06F11/22 ,  G06F11/36 ,  G06F12/06 ,  G06F15/78 ,  G06F9/455

CPC分类号： G06F11/3652 ,  G06F12/0646

摘要： A microcomputer for emulation which has been conventionally unusable when built-in RAM capacities are different, because an access to an internal function circuit is different in bus control, wait condition and the like from the access to an external memory area, and despite the above fact, which now becomes usable by including a built-in RAM 17, a higher address decoder (virtual RAM address decoder) for generating a virtual RAM address space corresponding to a plurality of virtual RAM capacities within a range in which installed capacity of the built-in RAM 17 is made a maximum value, and a RAM capacity selection flag 36 for specifying any one of a plurality of virtual RAM address spaces which can be generated by the higher address decoder 22.

摘要翻译： 在内置RAM容量不同的情况下，由于对内部功能电路的访问在总线控制，等待条件等的访问方面与外部存储区域的访问不同，所以通常不能使用的仿真微型计算机，尽管如此 事实上，现在可以通过包括内置RAM 17，更高地址解码器（虚拟RAM地址解码器）来生成与多个虚拟RAM容量相对应的虚拟RAM地址空间可用的范围，该范围内的内置RAM - 将RAM17设为最大值，以及RAM容量选择标志36，用于指定可由高地址解码器22产生的多个虚拟RAM地址空间中的任一个。