公开(公告)号：US20120011378A1

公开(公告)日：2012-01-12

申请号：US13180152

申请日：2011-07-11

申请人： Damian Dalton ,  Abhay Vadher ,  Andrew McCarthy ,  Christian Steger

发明人： Damian Dalton ,  Abhay Vadher ,  Andrew McCarthy ,  Christian Steger

IPC分类号： G06F1/00

CPC分类号： G06F11/3447 ,  G06F11/3062 ,  G06F11/328 ,  G06F11/3428 ,  G06F11/3466 ,  G06F2201/815 ,  Y02D10/34

摘要： Systems and methods for estimating power consumption in a network of computing devices are described. Operational information of a target server is periodically received and compared to benchmark data of a model of the target server. The operational information comprises performance data of the target server during a predefined time interval. Power consumption of the target server is estimated using the performance and benchmark data. The benchmark data is recalibrated if an error in the estimated power consumption is detected. An agent installed on the target server for collecting performance data is described. The target server can be a virtualized server, in which case, the agent acquires at least some of the performance data from a hypervisor of a physical server that hosts the target server.

摘要翻译： 描述用于估计计算设备的网络中的功率消耗的系统和方法。 定期接收目标服务器的操作信息，并将其与目标服务器型号的基准数据进行比较。 操作信息包括在预定时间间隔期间目标服务器的性能数据。 使用性能和基准数据估计目标服务器的功耗。 如果检测到估计的功耗错误，则重新校准基准数据。 描述安装在目标服务器上用于收集性能数据的代理。 目标服务器可以是虚拟化服务器，在这种情况下，代理从托管目标服务器的物理服务器的管理程序中获取至少一些性能数据。

公开(公告)号：US09170916B2

公开(公告)日：2015-10-27

申请号：US13180152

申请日：2011-07-11

申请人： Damian Dalton ,  Abhay Vadher ,  Andrew McCarthy ,  Christian Steger

发明人： Damian Dalton ,  Abhay Vadher ,  Andrew McCarthy ,  Christian Steger

IPC分类号： G06F1/00 ,  G01R21/00 ,  G06F11/34 ,  G06F11/30 ,  G06F11/32

CPC分类号： G06F11/3447 ,  G06F11/3062 ,  G06F11/328 ,  G06F11/3428 ,  G06F11/3466 ,  G06F2201/815 ,  Y02D10/34

摘要： Systems and methods for estimating power consumption in a network of computing devices are described. Operational information of a target server is periodically received and compared to benchmark data of a model of the target server. The operational information comprises performance data of the target server during a predefined time interval. Power consumption of the target server is estimated using the performance and benchmark data. The benchmark data is recalibrated if an error in the estimated power consumption is detected. An agent installed on the target server for collecting performance data is described. The target server can be a virtualized server, in which case, the agent acquires at least some of the performance data from a hypervisor of a physical server that hosts the target server.

摘要翻译： 描述用于估计计算设备的网络中的功率消耗的系统和方法。 定期接收目标服务器的操作信息，并将其与目标服务器型号的基准数据进行比较。 操作信息包括在预定时间间隔期间目标服务器的性能数据。 使用性能和基准数据估计目标服务器的功耗。 如果检测到估计的功耗错误，则重新校准基准数据。 描述安装在目标服务器上用于收集性能数据的代理。 目标服务器可以是虚拟化服务器，在这种情况下，代理从托管目标服务器的物理服务器的管理程序中获取至少一些性能数据。

公开(公告)号：US20070156380A1

公开(公告)日：2007-07-05

申请号：US11699015

申请日：2007-01-29

申请人： Damian Dalton

发明人： Damian Dalton

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A parallel processor for a logic event simulation (APPLES) including a main processor and an associative memory mechanism including a response resolver. Further, the associative memory mechanism includes a plurality of separate associative sub-registers each for storing in word form of a history of gate input signals for a specified type of logic gate, and a plurality of separate additional sub-registers associated with each associative sub-register whereby gate evaluations and tests can be carried out in parallel on each associative sub-register.

摘要翻译： 一种用于逻辑事件仿真（APPLES）的并行处理器，包括主处理器和包括响应解析器的关联存储器机制。 此外，关联存储器机构包括多个单独的关联子寄存器，每个子寄存器用于以字形式存储用于指定类型的逻辑门的门输入信号的历史，以及与每个关联子字段相关联的多个单独的附加子寄存器 注册，可以在每个关联子注册表上并行执行门评估和测试。

公开(公告)号：US20050228629A1

公开(公告)日：2005-10-13

申请号：US10505260

申请日：2002-02-22

申请人： Damian Dalton

发明人： Damian Dalton

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method and a processor for parallel processing of logic event simulation on circuits comprising a polarity of logic gates, the logic gates having interconnect lines therebetween, the processor (1) further comprising a main processor (2) and an associative memory mechanism (3), the associative memory mechanism (3) comprising a plurality of associative arrays (5, 6) and at least one result register, and there is provided accessible external memory (4) in which a circuit representation may be stored and divided into a plurality of segments, each of the segments having a segment identifier, which in turn has segment data associated therewith. The segment identifier and segment data being stored in a segment table (14) in the associative memory mechanism. Each of the segments may then be brought into the associative memory mechanism (3) for evaluation one at a time. There is additionally provided an amended result registering mechanism (8) to allow numerous tests and gate pairs to be carried out and recorded.

摘要翻译： 一种用于在包括逻辑门极性的电路上并行处理逻辑事件模拟的方法和处理器，所述逻辑门之间具有互连线，所述处理器还包括主处理器和关联存储器机构， ，所述关联存储器机构（3）包括多个关联阵列（5,6）和至少一个结果寄存器，并且提供可访问的外部存储器（4），其中电路表示可被存储并分成多个 段，每个段具有段标识符，其又具有与其相关联的段数据。 段标识符和段数据被存储在关联存储机构中的段表（14）中。 然后可以将每个段进入关联存储器机构（3），以一次一个地评估。 另外还提​​供了修改结果登记机制（8），以允许执行和记录许多测试和门对。