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    Semaphore access control buffer and method for accelerated semaphore operations
    3.
    发明授权
    Semaphore access control buffer and method for accelerated semaphore operations 失效
    信号量访问控制缓冲区和加速信号量操作的方法

    公开(公告)号：US5872980A

    公开(公告)日：1999-02-16

    申请号：US591290

    申请日：1996-01-25

    申请人： John E. Derrick ,  Christopher M. Herring

    发明人： John E. Derrick ,  Christopher M. Herring

    IPC分类号： G06F12/00 ,  G06F9/46 ,  G06F13/00

    CPC分类号： G06F9/52

    摘要： A spin buffer and associated method assure data integrity in shared resources in a computer system. Concurrent accesses to different semaphores by different devices are allowed. Lock and identification data within the semaphore is cached in the spin buffer so a device requesting access to a shared resource that corresponds to a semaphore that is represented in the spin buffer may determine whether any other device has ownership of the shared resource by accessing the data within the spin buffer, rather than reading from the semaphore. By caching semaphore lock information and allowing concurrent accesses to different semaphores by different devices, enhances system performance is achieved.

    摘要翻译： 自旋缓冲器和相关联的方法确保计算机系统中共享资源中的数据完整性。 允许通过不同设备同时访问不同的信号量。 信号量内的锁定和识别数据被缓存在自旋缓冲器中，所以请求访问对应于在自旋缓冲器中表示的信号量的共享资源的设备可以通过访问数据来确定是否有任何其他设备拥有共享资源的所有权 在旋转缓冲区内，而不是从信号量读取。 通过缓存信号锁信息并允许不同设备对不同信号量的并发访问，从而提高系统性能。

    Apparatus and method for decreasing the access time to non-cacheable address space in a computer system
    4.
    发明授权
    Apparatus and method for decreasing the access time to non-cacheable address space in a computer system 失效
    用于减少计算机系统中不可缓存地址空间的访问时间的装置和方法

    公开(公告)号：US5890216A

    公开(公告)日：1999-03-30

    申请号：US919578

    申请日：1997-08-28

    申请人： John E. Derrick ,  Christopher M. Herring

    发明人： John E. Derrick ,  Christopher M. Herring

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0888

    摘要： In a computer system, a multi-port bus controller interposed between a CPU, system memory, and an expansion bus detects when a CPU access is to non-cacheable address space and begins a bus cycle to access the data before receiving a "miss" from a cache coupled to the CPU. By detecting non-cacheable address space independently and in parallel with the cache miss determination, the multi-port bus controller saves from one to three clock cycles in each bus cycle that accesses non-cacheable address space.

    摘要翻译： 在计算机系统中，插入在CPU，系统存储器和扩展总线之间的多端口总线控制器检测在CPU访问是不可缓存地址空间的同时开始总线周期以在接收到“未命中”之前访问数据 从缓存耦合到CPU。 通过独立检测不可高速缓存的地址空间并与高速缓存未命中确定并行，多端口总线控制器在访问不可缓存地址空间的每个总线周期中节省一到三个时钟周期。

    Cache bus snoop protocol for optimized multiprocessor computer system
    5.
    发明授权
    Cache bus snoop protocol for optimized multiprocessor computer system 失效
    用于优化多处理器计算机系统的缓存总线侦听协议

    公开(公告)号：US5704058A

    公开(公告)日：1997-12-30

    申请号：US426503

    申请日：1995-04-21

    申请人： John E. Derrick ,  Christopher M. Herring

    发明人： John E. Derrick ,  Christopher M. Herring

    IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F13/38

    CPC分类号： G06F12/0831 ,  G06F12/0811

    摘要： A cache bus snoop protocol optimizes performance of a multiprocessor computer system with multiple level two caches by allocating windows of cache bus snoop activity on a need basis. When a cycle to cacheable address space is requested, the cache bus is granted only after the necessary snoop and write-back cycles are completed. During the snoop and write-back cycles, snoop activity by other devices in inhibited.

    摘要翻译： 缓存总线监听协议通过根据需要分配高速缓存总线监听活动的窗口来优化具有多级别高速缓存的多处理器计算机系统的性能。 当请求可缓存地址空间的周期时，只有在完成必要的监听和回写周期之后，才会授予高速缓存总线。 在窥探和回写周期中，其他设备的snoop活动被禁止。