公开(公告)号：US07291881B2

公开(公告)日：2007-11-06

申请号：US11592844

申请日：2006-11-02

申请人： Ronald Kakoschke ,  Danny Shum ,  Georg Tempel

发明人： Ronald Kakoschke ,  Danny Shum ,  Georg Tempel

IPC分类号： H01L29/76

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/66833

摘要： The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made via a covering connecting layer (12) and a self-aligning terminal layer (13) in an upper partial region of the trench.

公开(公告)号：US20060043420A1

公开(公告)日：2006-03-02

申请号：US10513163

申请日：2004-03-18

申请人： Ronald Kakoschke ,  Danny Shum ,  Georg Tempel

发明人： Ronald Kakoschke ,  Danny Shum ,  Georg Tempel

IPC分类号： H01L27/10

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/66833

摘要： The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made via a covering connecting layer (12) and a self-aligning terminal layer (13) in an upper partial region of the trench.

摘要翻译： 本发明涉及一种具有表面位线（DLx）和掩埋位线（SLx）的位线结构，埋入位线（SLx）形成在具有沟槽绝缘层（6）的沟槽中，并与掺杂 通过覆盖连接层（12）和沟槽的上部部分区域中的自对准端子层（13）与其接触的区域（10）。

公开(公告)号：US06909139B2

公开(公告)日：2005-06-21

申请号：US10607610

申请日：2003-06-27

申请人： Danny Shum ,  Georg Tempel ,  Ronald Kakoschke

发明人： Danny Shum ,  Georg Tempel ,  Ronald Kakoschke

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546

摘要： An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory array has floating gate transistors disposed in a triple well structure with a raised drain bit line 13 substantially vertically aligned with a buried source bit line 14. The memory array separates the columns with deep trenches 46 that may also be formed into charge pump capacitors.

摘要翻译： 集成电路具有高电压区域，逻辑区域和用于在包括线性，逻辑和存储器件的芯片上形成系统的存储器阵列。 存储器阵列具有布置在三阱结构中的浮置栅极晶体管，其高位漏极位线13基本上与掩埋源极线14垂直对准。 存储器阵列将列可以形成为电荷泵电容器的深沟槽46分离。

公开(公告)号：US07190022B2

公开(公告)日：2007-03-13

申请号：US11081886

申请日：2005-03-16

申请人： Danny Shum ,  Georg Tempel ,  Ronald Kakoschke

发明人： Danny Shum ,  Georg Tempel ,  Ronald Kakoschke

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546

摘要： An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory array has floating gate transistors disposed in a triple well structure with a raised drain bit line 13 substantially vertically aligned with a buried source bit line 14. The memory array separates the columns with deep trenches 46 that may also be formed into charge pump capacitors.

摘要翻译： 集成电路具有高电压区域，逻辑区域和存储器阵列，用于在包括线性，逻辑和存储器件的芯片上形成系统。 存储器阵列具有布置在三阱结构中的浮置栅极晶体管，其高位漏极位线13基本上与掩埋源极线14垂直对准。 存储器阵列将列可以形成为电荷泵电容器的深沟槽46分离。

公开(公告)号：US07176088B2

公开(公告)日：2007-02-13

申请号：US10513163

申请日：2004-03-18

申请人： Ronald Kakoschke ,  Danny Shum ,  Georg Tempel

发明人： Ronald Kakoschke ,  Danny Shum ,  Georg Tempel

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/66833

摘要： The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made via a covering connecting layer (12) and a self-aligning terminal layer (13) in an upper partial region of the trench.

摘要翻译： 本发明涉及一种具有表面位线（DLx）和掩埋位线（SLx）的位线结构，埋入位线（SLx）形成在具有沟槽绝缘层（6）的沟槽中，并与掺杂 通过覆盖连接层（12）和沟槽的上部部分区域中的自对准端子层（13）与其接触的区域（10）。

公开(公告)号：US20070049050A1

公开(公告)日：2007-03-01

申请号：US11592844

申请日：2006-11-02

申请人： Ronald Kakoschke ,  Danny Shum ,  Georg Tempel

发明人： Ronald Kakoschke ,  Danny Shum ,  Georg Tempel

IPC分类号： H01L21/31

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/66833

摘要： The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made via a covering connecting layer (12) and a self-aligning terminal layer (13) in an upper partial region of the trench.

摘要翻译： 本发明涉及一种具有表面位线（DLx）和掩埋位线（SLx）的位线结构，埋入位线（SLx）形成在具有沟槽绝缘层（6）的沟槽中，并与掺杂 通过覆盖连接层（12）和沟槽的上部部分区域中的自对准端子层（13）与其接触的区域（10）。

公开(公告)号：US20050180215A1

公开(公告)日：2005-08-18

申请号：US11081886

申请日：2005-03-16

申请人： Danny Shum ,  Georg Tempel ,  Ronald Kakoschke

发明人： Danny Shum ,  Georg Tempel ,  Ronald Kakoschke

IPC分类号： H01L21/8247 ,  H01L27/115 ,  G11C16/06

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546

摘要： An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory array has floating gate transistors disposed in a triple well structure with a raised drain bit line 13 substantially vertically aligned with a buried source bit line 14. The memory array separates the columns with deep trenches 46 that may also be formed into charge pump capacitors.

公开(公告)号：US20060131637A1

公开(公告)日：2006-06-22

申请号：US11273668

申请日：2005-11-14

申请人： Ronald Kakoschke ,  Franz Schuler ,  Georg Tempel

发明人： Ronald Kakoschke ,  Franz Schuler ,  Georg Tempel

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11521

摘要： The disclosure relates to a bit line structure and an associated production method for the bit line structure. In the bit line structure, at least in a region of a second contact and a plurality of first contact adjoining the latter, an isolation trench is filled with an electrically conductive trench filling layer. The isolation trench connects to the first doping regions adjoining the second contact for the purpose of realizing a buried contact bypass line.

摘要翻译： 本公开涉及位线结构和相关联的位线结构的制造方法。 在位线结构中，至少在第二触点的区域和与其相邻的多个第一触点的区域中，隔离沟槽填充有导电沟槽填充层。 隔离沟槽连接到与第二接触相邻的第一掺杂区域，以实现埋地接触旁路线路。

公开(公告)号：US20060108692A1

公开(公告)日：2006-05-25

申请号：US11273595

申请日：2005-11-14

申请人： Ronald Kakoschke ,  Franz Schuler ,  Georg Tempel

发明人： Ronald Kakoschke ,  Franz Schuler ,  Georg Tempel

IPC分类号： H01L23/52

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11521

摘要： A bit line structure and associated fabrication method are provided for a semiconductor element or circuit arrangement. The bit line structure contains a surface bit line and a buried bit line. The buried bit line is formed in an upper section of a trench and is connected to an associated first doping region via a first connection layer. A first trench filling layer, which is insulated from the buried bit line by a second trench insulating layer, is situated in a lower section of the trench.

摘要翻译： 为半导体元件或电路布置提供了位线结构和相关联的制造方法。 位线结构包含表面位线和掩埋位线。 掩埋位线形成在沟槽的上部，并且经由第一连接层连接到相关联的第一掺杂区域。 通过第二沟槽绝缘层与掩埋位线绝缘的第一沟槽填充层位于沟槽的下部。

公开(公告)号：US08193059B2

公开(公告)日：2012-06-05

申请号：US12695277

申请日：2010-01-28

申请人： Ronald Kakoschke ,  Franz Schuler ,  Georg Tempel

发明人： Ronald Kakoschke ,  Franz Schuler ,  Georg Tempel

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11521

摘要： A bit line structure and associated fabrication method are provided for a semiconductor element or circuit arrangement. The bit line structure contains a surface bit line and a buried bit line. The buried bit line is formed in an upper section of a trench and is connected to an associated first doping region via a first connection layer. A first trench filling layer, which is insulated from the buried bit line by a second trench insulating layer, is situated in a lower section of the trench.

摘要翻译： 为半导体元件或电路布置提供了位线结构和相关联的制造方法。 位线结构包含表面位线和掩埋位线。 掩埋位线形成在沟槽的上部，并且经由第一连接层连接到相关联的第一掺杂区域。 通过第二沟槽绝缘层与掩埋位线绝缘的第一沟槽填充层位于沟槽的下部。