公开(公告)号：US07855969B2

公开(公告)日：2010-12-21

申请号：US11136236

申请日：2005-05-24

申请人： Danny Vogel ,  Bryan Robb ,  Robert F Smith

发明人： Danny Vogel ,  Bryan Robb ,  Robert F Smith

IPC分类号： G01R31/08

CPC分类号： G01R31/31715 ,  G01R31/31716

摘要： The present invention is directed to a method and system for testing systems involving high speed SERDES cores by exposing an internal nature of signals. The signals are tapped at various external test points. The present invention may take one or more test points in receive and/or transmit paths of high speed SERDES cores, and expose the test points by routing signals to the pins/balls on a chip. Programmable directing (multiplexing) of signals may be utilized to restrict number of output debug ports. Consequently, the number of the pin count required for the chip may be controlled.

摘要翻译： 本发明涉及一种用于通过暴露信号的内部特性来测试涉及高速SERDES内核的系统的方法和系统。 信号在各种外部测试点被点击。 本发明可以在高速SERDES内核的接收和/或发送路径中采用一个或多个测试点，并通过将信号路由到芯片上的引脚/球来暴露测试点。 信号的可编程定向（多路复用）可以用于限制输出调试端口的数量。 因此，可以控制芯片所需的引脚数目。