公开(公告)号：US07855969B2

公开(公告)日：2010-12-21

申请号：US11136236

申请日：2005-05-24

申请人： Danny Vogel ,  Bryan Robb ,  Robert F Smith

发明人： Danny Vogel ,  Bryan Robb ,  Robert F Smith

IPC分类号： G01R31/08

CPC分类号： G01R31/31715 ,  G01R31/31716

摘要： The present invention is directed to a method and system for testing systems involving high speed SERDES cores by exposing an internal nature of signals. The signals are tapped at various external test points. The present invention may take one or more test points in receive and/or transmit paths of high speed SERDES cores, and expose the test points by routing signals to the pins/balls on a chip. Programmable directing (multiplexing) of signals may be utilized to restrict number of output debug ports. Consequently, the number of the pin count required for the chip may be controlled.

摘要翻译： 本发明涉及一种用于通过暴露信号的内部特性来测试涉及高速SERDES内核的系统的方法和系统。 信号在各种外部测试点被点击。 本发明可以在高速SERDES内核的接收和/或发送路径中采用一个或多个测试点，并通过将信号路由到芯片上的引脚/球来暴露测试点。 信号的可编程定向（多路复用）可以用于限制输出调试端口的数量。 因此，可以控制芯片所需的引脚数目。

公开(公告)号：US06931027B1

公开(公告)日：2005-08-16

申请号：US09624816

申请日：2000-07-25

申请人： Danny Vogel ,  Bryan Robb ,  Clinton Seeman

发明人： Danny Vogel ,  Bryan Robb ,  Clinton Seeman

IPC分类号： H04J3/18 ,  H04L25/45

CPC分类号： H04L25/45

摘要： In a Framed Packet Bus (FPB) serial bus, an improved protocol and circuit layout for communication between devices grounded in the same chassis or chip. The improved protocol eliminates the requirement that bits have DC balance in their HIGH and LOW voltage levels. Consequently, bus overhead is reduced over prior techniques. In one example, data capacity utilization was increased from 80% to 95% and bus overhead was reduced from 20% to 5%. As a result of increased capacity, more packets of data may be carried across the serial bus, and any leftover bits within the frame cycle and in subsequent cycles may carry error detection information or be utilized as a control for the bus. In one preferred embodiment, the FPB serial bus configuration consists of sixteen serial lines arranged in parallel.

摘要翻译： 在帧分组总线（FPB）串行总线中，改进的协议和电路布局用于在同一机箱或芯片上接地的设备之间进行通信。 改进的协议消除了在高电平和低电平电平下具有直流平衡的要求。 因此，总线开销比现有技术减少。 在一个例子中，数据容量利用率从80％提高到95％，总线开销从20％下降到5％。 作为增加容量的结果，可以在串行总线上携带更多的数据包，并且在帧周期内和随后的周期中的任何剩余位可以携带错误检测信息或用作总线的控制。 在一个优选实施例中，FPB串行总线配置由并行布置的十六个串行线组成。

公开(公告)号：US20060268723A1

公开(公告)日：2006-11-30

申请号：US11136236

申请日：2005-05-24

申请人： Danny Vogel ,  Bryan Robb ,  Robert Smith

发明人： Danny Vogel ,  Bryan Robb ,  Robert Smith

IPC分类号： H04L12/26 ,  H04J1/16

CPC分类号： G01R31/31715 ,  G01R31/31716

摘要： The present invention is directed to a method and system for testing systems involving high speed SERDES cores by exposing an internal nature of signals. The signals are tapped at various external test points. The present invention may take one or more test points in receive and/or transmit paths of high speed SERDES cores, and expose the test points by routing signals to the pins/balls on a chip. Programmable directing (multiplexing) of signals may be utilized to restrict number of output debug ports. Consequently, the number of the pin count required for the chip may be controlled.

摘要翻译： 本发明涉及一种用于通过暴露信号的内部特性来测试涉及高速SERDES内核的系统的方法和系统。 信号在各种外部测试点被点击。 本发明可以在高速SERDES内核的接收和/或发送路径中采用一个或多个测试点，并通过将信号路由到芯片上的引脚/球来暴露测试点。 信号的可编程定向（多路复用）可以用于限制输出调试端口的数量。 因此，可以控制芯片所需的引脚数目。