公开(公告)号：US5857117A

公开(公告)日：1999-01-05

申请号：US577866

申请日：1995-12-22

申请人： Darren Abramson ,  Joe A. Bennett

发明人： Darren Abramson ,  Joe A. Bennett

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4022

摘要： A transceiver as provided for effectively multiplexing IDE address and data lines with selected ISA address and data lines. Compatibility among the IDE data transfers and ISA functions are achieved by multiplexing the ISA lines that do not involve the ISA refresh of the ISA expanded memory. The transceiver includes an enable input that, when disabled, effectively isolates the IDE data lines from the ISA bus so that IDE data transfers can occur. When the enable input is active, the ISA lines not related to refresh are connected to the IDE data lines so that ISA operations can occur. Furthermore, a directional input is included in the transceiver for allowing a central processing unit to control the ISA when the directional input is active and for allowing a PCI/ISA bridge between the PCI bus and the ISA bus to control the ISA operations included the multiplexing. The result is a rearrangement of the IDE data lines with the ISA bus to eliminate a multitude of pins and connectors.

摘要翻译： 提供的收发器，用于有效地复用IDE地址和数据线与选定的ISA地址和数据线。 IDE数据传输和ISA功能之间的兼容性是通过复用不涉及ISA扩展内存的ISA刷新的ISA线来实现的。 收发器包括一个使能输入，当被禁用时，有效地将IDE数据线与ISA总线隔离，以便可以发生IDE数据传输。 当启用输入处于活动状态时，与刷新无关的ISA线路连接到IDE数据线，以便可以进行ISA操作。 此外，收发器中包括方向输入，用于当方向输入有效时允许中央处理单元控制ISA，并允许PCI总线与ISA总线之间的PCI / ISA桥控制包括复用的ISA操作 。 结果是IDE数据线与ISA总线重新排列，以消除大量的引脚和连接器。