公开(公告)号：US5491659A

公开(公告)日：1996-02-13

申请号：US372480

申请日：1995-01-13

Applicant: Dave Howarter ,  George Wiley

Inventor： Dave Howarter ,  George Wiley

IPC: G06F5/10 ,  G06F5/14 ,  G11C7/00

CPC classification number: G06F5/14 ,  G06F2205/102

Abstract: In a first-in-first out memory, at least one data item is stored, and a write counter is incremented in response to the storing of each data item as it is stored into the memory. A full condition counter is also incremented in response to the writing of each data item. The at least one data item is also read from the memory, and a read counter is incremented in response to the reading of each data item from the memory. An empty condition counter is also incremented in response to the reading of each data item from the memory. In order to assure that the empty and full flag signals are not generated simultaneously, the full flag signal is generated in response to a count within the full condition counter that leads a count within the empty condition counter by a first prescribed difference. The empty flag signal is generated in response to the count within the full condition counter lagging the count within the empty condition counter by a second prescribed difference. As a result, the full flag signal and the empty flag signal are never simultaneously generated so long as the full condition counter and the empty condition counter each have at least one more state than the read counter and the write counter.

Abstract translation: 在先进先出存储器中，存储至少一个数据项，并且响应于存储在存储器中的每个数据项的存储而增加写计数器。 响应于每个数据项的写入，全状态计数器也递增。 还从存储器读取至少一个数据项，并且响应于从存储器读取每个数据项而增加读计数器。 响应于从存储器读取每个数据项，空条件计数器也递增。 为了确保空标志信号和全标志信号不同时产生，响应于在空状态计数器内的计数引起第一规定差的全状态计数器内的计数，产生全标志信号。 响应于在完全状态计数器内的计数使空条件计数器中的计数器滞后第二规定的差值而产生空标志信号。 结果，只要全状态计数器和空状态计数器都具有比读计数器和写计数器至少多一个状态，则不会同时产生全标志信号和空标志信号。