公开(公告)号：US5491659A

公开(公告)日：1996-02-13

申请号：US372480

申请日：1995-01-13

Applicant: Dave Howarter ,  George Wiley

Inventor： Dave Howarter ,  George Wiley

IPC: G06F5/10 ,  G06F5/14 ,  G11C7/00

CPC classification number: G06F5/14 ,  G06F2205/102

Abstract: In a first-in-first out memory, at least one data item is stored, and a write counter is incremented in response to the storing of each data item as it is stored into the memory. A full condition counter is also incremented in response to the writing of each data item. The at least one data item is also read from the memory, and a read counter is incremented in response to the reading of each data item from the memory. An empty condition counter is also incremented in response to the reading of each data item from the memory. In order to assure that the empty and full flag signals are not generated simultaneously, the full flag signal is generated in response to a count within the full condition counter that leads a count within the empty condition counter by a first prescribed difference. The empty flag signal is generated in response to the count within the full condition counter lagging the count within the empty condition counter by a second prescribed difference. As a result, the full flag signal and the empty flag signal are never simultaneously generated so long as the full condition counter and the empty condition counter each have at least one more state than the read counter and the write counter.

Abstract translation: 在先进先出存储器中，存储至少一个数据项，并且响应于存储在存储器中的每个数据项的存储而增加写计数器。 响应于每个数据项的写入，全状态计数器也递增。 还从存储器读取至少一个数据项，并且响应于从存储器读取每个数据项而增加读计数器。 响应于从存储器读取每个数据项，空条件计数器也递增。 为了确保空标志信号和全标志信号不同时产生，响应于在空状态计数器内的计数引起第一规定差的全状态计数器内的计数，产生全标志信号。 响应于在完全状态计数器内的计数使空条件计数器中的计数器滞后第二规定的差值而产生空标志信号。 结果，只要全状态计数器和空状态计数器都具有比读计数器和写计数器至少多一个状态，则不会同时产生全标志信号和空标志信号。

公开(公告)号：US08496547B2

公开(公告)日：2013-07-30

申请号：US12958212

申请日：2010-12-01

Applicant: George Wiley

Inventor： George Wiley

IPC: A63B63/00

CPC classification number: A63B63/008 ,  A63B2071/009 ,  A63B2210/50

Abstract: A collapsible goal post includes a lower support extending from a playing field; a upper support having a first end and a second end, and a pivot assembly attaching the first end of the upper support to the lower support; an upper assembly comprising two uprights and a crossbar having two ends. The crossbar is attached to the second end of the support at about the midpoint of the crossbar. One of the two uprights is attached to each end of the crossbar. The upper support is configured to pivot about the pivot point assembly to move the upright assembly from a raised position to a lowered position. The two uprights are substantially perpendicular to the playing field in the raised position, and are substantially parallel to and contacting the playing field in the lowered position while the upper assembly and upper support remain attached to the lower support. In another embodiment, the goal post includes a hydraulic cylinder system coupled to the upper support and the lower support to hinder a rate of pivoting of the goal post about the pivot assembly.

Abstract translation: 可折叠的目标岗位包括从游戏场延伸的较低支撑; 具有第一端和第二端的上支撑件和枢轴组件，所述枢轴组件将所述上支撑件的第一端附接到所述下支撑件; 包括两个立柱的上部组件和具有两个端部的横杆。 横杆在横杆的中点附近附接到支撑件的第二端。 两个立柱之一附在横梁的每一端。 上支撑件构造成围绕枢轴点组件枢转以将直立组件从升高位置移动到降低位置。 两个立柱基本上垂直于升高位置的运动场，并且在上部组件和上部支撑件保持附接到下部支撑件的同时基本上平行于并接触下降位置的运动场。 在另一个实施例中，目标柱包括联接到上支撑件和下支撑件的液压缸系统，以阻止球杆柱绕枢转组件枢转的速率。

公开(公告)号：US20060034326A1

公开(公告)日：2006-02-16

申请号：US11107536

申请日：2005-04-14

Applicant: Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

Inventor： Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

IPC: H04J3/16

CPC classification number: H04L69/22 ,  H04L69/18 ,  H04M1/72527 ,  Y02D70/144 ,  Y02D70/26

Abstract: A data interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

公开(公告)号：US20050117601A1

公开(公告)日：2005-06-02

申请号：US10917930

申请日：2004-08-12

Applicant: Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

Inventor： Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

IPC: G06F13/40 ,  H04L12/56 ,  H04L29/00 ,  H04L29/06 ,  H04M1/725

CPC classification number: G06F13/4072 ,  H04L29/06027 ,  H04L65/607 ,  H04L69/22 ,  H04M1/72527 ,  Y02D70/00 ,  Y02D70/122 ,  Y02D70/1262 ,  Y02D70/144 ,  Y02D70/26

Abstract: A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

Abstract translation: 一种数据接口，用于通过连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据，以形成用于传送预先选择的一组数字控制和呈现数据的通信协议。 信号协议被配置为生成，发送和接收形成通信协议的分组的链路控制器使用，并且将数字数据形成为一个或多个类型的数据分组，其中至少一个驻留在主机设备中并耦合到 客户端通过通信路径。 该接口通过短距离“串行”类型数据链路提供了经济高效，低功耗，双向，高速的数据传输机制，可实现微型连接器和薄型柔性电缆，特别适用于 将可穿戴式微型显示器等显示元件连接到便携式计算机和无线通信装置。

公开(公告)号：US20050021885A1

公开(公告)日：2005-01-27

申请号：US10860116

申请日：2004-06-02

Applicant: Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

Inventor： Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

IPC: H04L1/00 ,  H04L1/24 ,  H04L7/00 ,  H04L7/04 ,  H04L7/10 ,  H04L29/06 ,  H04L29/08 ,  H04M1/725 ,  H04N7/24 ,  G06F3/00

CPC classification number: H04L65/607 ,  H04L1/0061 ,  H04L1/245 ,  H04L7/0008 ,  H04L7/048 ,  H04L7/10 ,  H04L29/06 ,  H04L29/06027 ,  H04L69/03 ,  H04L69/18 ,  H04L69/22 ,  H04L69/24 ,  H04L69/324 ,  H04M1/72527 ,  H04N21/4122 ,  H04N21/41407 ,  H04N21/43632 ,  Y02D70/122 ,  Y02D70/26

Abstract: A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

Abstract translation: 一种数据接口，用于通过连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据，以形成用于传送预先选择的一组数字控制和呈现数据的通信协议。 信号协议被配置为生成，发送和接收形成通信协议的分组的链路控制器使用，并且将数字数据形成为一个或多个类型的数据分组，其中至少一个驻留在主机设备中并耦合到 客户端通过通信路径。 该接口通过短距离“串行”类型数据链路提供了经济高效，低功耗，双向，高速的数据传输机制，可实现微型连接器和薄型柔性电缆，特别适用于 将可穿戴式微型显示器等显示元件连接到便携式计算机和无线通信装置。

公开(公告)号：US08848810B2

公开(公告)日：2014-09-30

申请号：US12042362

申请日：2008-03-05

Applicant: Chulkyul Lee ,  Anosh Davierwalla ,  George Wiley

Inventor： Chulkyul Lee ,  Anosh Davierwalla ,  George Wiley

IPC: H04K1/10 ,  H04B14/04 ,  H04L12/28 ,  H04L25/02 ,  H04L25/49

CPC classification number: H04L25/0272 ,  H04L25/49

Abstract: Systems and methods of data transmission are disclosed. In an embodiment, at least two transmitters are selectively activated and at least one transmitter is deactivated at a serial interface to transmit data via at least two distinct lines.

Abstract translation: 公开了数据传输的系统和方法。 在一个实施例中，选择性地激活至少两个发射机，并且至少一个发射机在串行接口处被去激活，以经由至少两条不同的线路传输数据。

公开(公告)号：US20080088492A1

公开(公告)日：2008-04-17

申请号：US11937913

申请日：2007-11-09

Applicant: George Wiley ,  Brian Steele ,  Curtis Musfeldt

Inventor： George Wiley ,  Brian Steele ,  Curtis Musfeldt

IPC: H03M7/00

CPC classification number: H03M7/16

Abstract: A double data rate serial encoder is provided. The serial encoder comprises a mux having a plurality of inputs, a plurality of latches coupled to the inputs of the mux, an enabler to enable the latches to update their data inputs, and a counter to select one of the plurality of inputs of the mux for output. In another aspect, the mux provides a glitch-less output during input transitions. The mux includes an output selection algorithm optimized based on a priori knowledge of an input selection sequence provided by the counter.

Abstract translation: 提供双数据速率串行编码器。 串行编码器包括具有多个输入的多路复用器，耦合到多路复用器的输入的多个锁存器，使得锁存器能够更新其数据输入的启动器，以及用于选择多路复用器的多个输入之一的计数器 用于输出。 在另一方面，多路复用器在输入转换期间提供无毛刺输出。 多路复用器包括基于由计数器提供的输入选择序列的先验知识而优化的输出选择算法。

公开(公告)号：US20060164424A1

公开(公告)日：2006-07-27

申请号：US11285399

申请日：2005-11-23

Applicant: George Wiley ,  Brian Steele

Inventor： George Wiley ,  Brian Steele

IPC: G09G5/399

CPC classification number: G09G5/393 ,  G09G5/006

Abstract: The present invention relates to methods and systems for updating a buffer. In one aspect, the present invention provides a method for updating a buffer, which includes strategically writing to the buffer to enable concurrent read and write to the buffer. The method eliminates the need for double buffering, thereby resulting in implementation cost and space savings compared to conventional buffering approaches. The method also prevents image tearing when used to update a frame buffer associated with a display, but is not limited to such applications. In another aspect, the present invention provides efficient mechanisms to enable buffer update across a communication link. In one example, the present invention provides a method for relaying timing information across a communication link.

Abstract translation: 本发明涉及用于更新缓冲器的方法和系统。 一方面，本发明提供了一种用于更新缓冲器的方法，其包括对缓冲器进行战略性地写入，以实现对缓冲器的并发读取和写入。 该方法消除了对双缓冲的需要，从而与常规缓冲方法相比，导致实现成本和空间节省。 当用于更新与显示器相关联的帧缓冲器时，该方法还防止图像撕裂，但不限于此类应用。 在另一方面，本发明提供了有效的机制来实现跨越通信链路的缓冲器更新。 在一个示例中，本发明提供了一种用于在通信链路上中继定时信息的方法。

公开(公告)号：US20060034301A1

公开(公告)日：2006-02-16

申请号：US11096855

申请日：2005-03-31

Applicant: Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

Inventor： Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

IPC: H04L12/56

CPC classification number: H04W88/02 ,  H04L69/18 ,  H04L69/22 ,  H04M1/72527 ,  Y02D70/144 ,  Y02D70/26

Abstract: A data interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

Abstract translation: 一种数据接口，用于通过连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据，以形成用于传送预先选择的一组数字控制和呈现数据的通信协议。 信号协议被配置为生成，发送和接收形成通信协议的分组的链路控制器使用，并且将数字数据形成为一个或多个类型的数据分组，其中至少一个驻留在主机设备中并耦合到 客户端通过通信路径。 该接口通过短距离“串行”型数据链路提供了经济高效，低功耗，双向，高速的数据传输机制，可实现微型连接器和薄型柔性电缆，这些电缆特别适用于 将可穿戴式微型显示器等显示元件连接到便携式计算机和无线通信装置。

公开(公告)号：US08364857B2

公开(公告)日：2013-01-29

申请号：US12551530

申请日：2009-08-31

Applicant: James Pyers ,  George Wiley ,  James J. Willkie ,  Brian Steele ,  Apul Nahata ,  Karthik Raj Kaliannan

Inventor： James Pyers ,  George Wiley ,  James J. Willkie ,  Brian Steele ,  Apul Nahata ,  Karthik Raj Kaliannan

IPC: G06F3/00 ,  G06F12/00

CPC classification number: G06F1/3203 ,  G06F1/3293 ,  Y02D10/122

Abstract: A computing device includes a low power auxiliary processor, such as a processor on a wireless card or sub-system, which is able to takeover processing in place of the computing device's central processing unit (CPU). Operating the computing device on the auxiliary processor draws less power from the computing device battery, enabling extended operation in an auxiliary processor mode. When in this mode, the auxiliary processor controls peripherals and provides the system functionality while the CPU is deactivated, such as in “off,” “standby” or “sleep” modes. In the auxiliary processor mode, the computing device can accomplish useful tasks, such as sending/receiving electronic mail, displaying electronic documents and accessing a network while drawing minimal power from the battery. Transitions between the normal operating mode and auxiliary processor mode may be transparent to users. Such a computer may display instant on, always on and always connected operating features.

Abstract translation: 计算设备包括能够接管处理代替计算设备的中央处理单元（CPU）的低功率辅助处理器，诸如无线卡或子系统上的处理器。 在辅助处理器上操作计算设备从计算设备电池吸取更少的电力，从而能够在辅助处理器模式下进行扩展操作。 在此模式下，辅助处理器控制外设，并在CPU被关闭时提供系统功能，例如关闭，待机或休眠模式。 在辅助处理器模式中，计算设备可以完成有用的任务，例如发送/接收电子邮件，显示电子文档和访问网络，同时从电池中抽取最小功率。 正常操作模式和辅助处理器模式之间的转换可能对用户来说是透明的。 这样的计算机可以立即显示，始终处于和始终连接的操作特征。