公开(公告)号：US4810925A

公开(公告)日：1989-03-07

申请号：US47106

申请日：1987-05-08

Applicant: David B. Fox

Inventor： David B. Fox

IPC: H01J1/15 ,  H01J23/04 ,  H01J23/05 ,  H01J1/13

CPC classification number: H01J23/05

Abstract: A directly heated cathode comprises a metal tube having a filling of powdered metal which extends beyond the tube and in which is embedded an electrical wire which is coaxial and extensive with said the outer tube over part of its length. The electrical wire is coated with insulating material which is normally alumina. The tube, the metal powder filling and the wire are sintered together, giving a relatively robust structure.

Abstract translation: 直接加热的阴极包括金属管，其具有延伸超过管的粉末金属的填充物，并且其中嵌入有与所述外管在其一部分长度上同轴且广泛的电线。 电线涂有绝缘材料，绝缘材料通常是氧化铝。 管，金属粉末填充物和线被烧结在一起，给出相对坚固的结构。

公开(公告)号：US08149833B2

公开(公告)日：2012-04-03

申请号：US11137606

申请日：2005-05-24

Applicant: David B. Fox ,  John T. Chapman ,  Alon S. Bernstein ,  Albert A. Slane

Inventor： David B. Fox ,  John T. Chapman ,  Alon S. Bernstein ,  Albert A. Slane

IPC: H04L12/28 ,  H04J3/24

CPC classification number: H04N21/6118 ,  H04L69/14 ,  H04L69/22 ,  H04N7/17309 ,  H04N21/6168

Abstract: A network device has a communications port to provide communication with a data network and a cable port to provide communication with a cable network across multiple channels. The network device also has a processor to receive data from the data network, format the data into packets for transmission across the multiple channels and provide an identifier to allow the packets to be reconstructed.

Abstract translation: 网络设备具有通信端口以提供与数据网络和电缆端口的通信，以在多个信道上提供与有线网络的通信。 网络设备还具有处理器，用于从数据网络接收数据，将数据格式化成分组以在多个信道上传输，并提供标识符以允许分组被重建。

公开(公告)号：US07139963B1

公开(公告)日：2006-11-21

申请号：US10439059

申请日：2003-05-15

Applicant: David B. Fox

Inventor： David B. Fox

IPC: H03M13/00

CPC classification number: H03M13/091 ,  H03M13/6575 ,  H04L1/0052 ,  H04L1/0057 ,  H04L1/0061

Abstract: A given data packet is parsed into words and a final partial word that are processed (depending on size) in each of multiple successive stages of logic circuitry. Similarly sized words are processed at one stage of the logic circuit. Smaller and smaller modulo-2 components of the final partial word are processed at successive stages of logic circuitry. Based on this technique of processing modulo-2 components in different stages, the corresponding multi-stage logic circuit can be implemented in a low cost logic circuit such as an FPGA device instead of a custom-masked ASIC.

Abstract translation: 一个给定的数据包被解析为字和在逻辑电路的多个连续阶段的每一个中被处理（取决于大小）的最后的部分字。 类似大小的字在逻辑电路的一个阶段被处理。 在逻辑电路的连续阶段处理最终部分字的较小和较小的模2分量。 基于在不同阶段处理模2分量的这种技术，相应的多级逻辑电路可以在诸如FPGA器件的低成本逻辑电路中而不是定制掩蔽的ASIC中实现。

公开(公告)号：US07720101B2

公开(公告)日：2010-05-18

申请号：US11134659

申请日：2005-05-20

Applicant: John T. Chapman ,  David B. Fox ,  Albert A. Slane

Inventor： John T. Chapman ,  David B. Fox ,  Albert A. Slane

IPC: H04J1/00 ,  H04J3/16 ,  H04N7/173

CPC classification number: H04L12/2801

Abstract: A hybrid cable modem includes wideband circuitry configured to receive data over multiple different downstream channels at the same time. The wideband circuitry demodulates signals on the different downstream channels and then formats the demodulated signals back into packets or frames for sending out over an Internet Protocol (IP) home network. Narrowband cable modem circuitry is coupled to the wideband circuitry and selectively extracts Data Over Cable Service Interface Specifications (DOCSIS) data from one of the multiple downstream channels being processed by the wideband circuitry.

Abstract translation: 混合电缆调制解调器包括配置成同时在多个不同下游信道上接收数据的宽带电路。 宽带电路解调不同下游信道上的信号，然后将解调的信号格式化成分组或帧，以通过因特网协议（IP）家庭网络发送。 窄带电缆调制解调器电路耦合到宽带电路，并且从宽带电路处理的多个下游信道中的一个有选择地提取数据通过电缆服务接口规范（DOCSIS）数据。

公开(公告)号：US07688828B2

公开(公告)日：2010-03-30

申请号：US11134589

申请日：2005-05-17

Applicant: John T. Chapman ,  Daniel W. Crocker ,  Alon S. Bernstein ,  Michael J. Healy ,  David B. Fox

Inventor： John T. Chapman ,  Daniel W. Crocker ,  Alon S. Bernstein ,  Michael J. Healy ,  David B. Fox

IPC: H04L12/28 ,  H04L12/56 ,  H04J3/16 ,  H04J3/22 ,  H04J1/00 ,  H04N7/173 ,  H04N7/16

CPC classification number: H04L12/2801 ,  H04L67/00 ,  H04L69/16 ,  H04L69/161 ,  H04L69/164 ,  H04L2212/00

Abstract: A modular Cable Modem Termination System (CMTS) includes a packet shelf operating a Data Over Cable Service Interface Specifications (DOCSIS) Media Access Control (MAC) framer. One or more downstream Physical Interface (PHY) shelves receive DOCSIS data from the packet shelf over a packet switched network and modulate the DOCSIS data for sending on a downstream path of a cable plant. One or more upstream PHY shelves send DOCSIS data received from an upstream path of the cable plant over the packet switched network to the packet shelf. By separating the PHY components from the MAC and from the system software, the PHY components for a Hybrid Fiber Coax (HFC) plant may be replaced with different PHY components for other access technologies such as wireless, Digital Subscriber Lines (DSL), Ethernet-to-the-Home, Fiber-to-the-Home, or fiber Passive Optical Networks (PONs).

Abstract translation: 模块化电缆调制解调器终端系统（CMTS）包括操作数据有线业务接口规范（DOCSIS）媒体接入控制（MAC）成帧器的分组机架。 一个或多个下行物理接口（PHY）机架通过分组交换网络从分组机架接收DOCSIS数据，并且调制DOCSIS数据以在电缆设备的下游路径上发送。 一个或多个上游PHY层架将从电缆设备的上行路径接收的DOCSIS数据通过分组交换网络发送到分组架。 通过将PHY组件与MAC和系统软件分离，用于混合光纤同轴电缆（HFC）设备的PHY组件可以用于其他接入技术的不同PHY组件，例如无线，数字用户线（DSL），以太网 - 光纤到户或光纤无源光网络（PON）。

公开(公告)号：US06931492B2

公开(公告)日：2005-08-16

申请号：US10003857

申请日：2001-11-02

Applicant: David B. Fox ,  Joseph M. Hoke ,  Tin-Chee Lo

Inventor： David B. Fox ,  Joseph M. Hoke ,  Tin-Chee Lo

IPC: G06F11/34 ,  G06F11/36 ,  G06F12/08 ,  G06F12/00

CPC classification number: G06F11/3636 ,  G06F11/348 ,  G06F12/0802 ,  G06F2201/885 ,  G06F2212/2515

Abstract: A method is disclosed for instructing a computing system to allocate a trace array from an original cache memory, where the method includes dividing the original cache memory into a reduced-size cache memory and a trace array, permitting storage of trace signal data into the trace array, and permitting retrieval of the trace signal data from the trace array.

Abstract translation: 公开了一种用于指示计算系统从原始高速缓冲存储器分配跟踪阵列的方法，其中该方法包括将原始高速缓存存储器分为缩小大小的高速缓冲存储器和跟踪阵列，允许将跟踪信号数据存储到跟踪中 阵列，并允许从跟踪数组中检索跟踪信号数据。