公开(公告)号：US5530809A

公开(公告)日：1996-06-25

申请号：US181711

申请日：1994-01-14

申请人： David C. Douglas ,  Charles E. Leiserson ,  Bradley C. Kuszmaul ,  Shaw-Wen Yang ,  W. Daniel Hillis ,  David Wells ,  Carl R. Feynman ,  Bruce J. Walker ,  Brewster Kahle

发明人： David C. Douglas ,  Charles E. Leiserson ,  Bradley C. Kuszmaul ,  Shaw-Wen Yang ,  W. Daniel Hillis ,  David Wells ,  Carl R. Feynman ,  Bruce J. Walker ,  Brewster Kahle

IPC分类号： G06F15/16 ,  G06F11/00 ,  G06F11/08 ,  G06F11/22 ,  G06F15/173 ,  G06F15/80 ,  G06F15/163

CPC分类号： G06F15/17381 ,  G06F11/08 ,  G06F11/22 ,  G06F11/324 ,  G06F15/17343 ,  H04L45/48 ,  H04L49/35 ,  H04L49/555 ,  G06F2201/88

摘要： A digital computer comprising a plurality of message generating nodes interconnected by a routing network. The routing network transfers messages among the message generating elements in accordance with address information identifying a destination message generating element. Each message generating node includes a message data generator and a network interface. The message data generator generates message data items each including an address data portion comprising a destination identifier. The network interface includes a message generator and an address translation table, the table including a plurality of entries identifying, for at least one destination identifier, a translated destination identifier. The message generator, in response to the receipt of a message data item from the message data generator, generates a message for transmission to the routing network. In generating the message, the message generator performs an address translation operation in connection with the address data and the contents of the address translation table to generate updated address data which it uses data in connection with generating address information for the message.

摘要翻译： 一种数字计算机，包括由路由网络互连的多个消息生成节点。 路由网络根据识别目的地消息生成元素的地址信息在消息生成元件之间传送消息。 每个消息生成节点包括消息数据生成器和网络接口。 消息数据生成器生成包括包括目的地标识符的地址数据部分的消息数据项。 网络接口包括消息发生器和地址转换表，该表包括多个条目，用于为至少一个目的地标识符标识已翻译的目的地标识符。 消息生成器响应于从消息数据生成器接收到消息数据项，生成用于传输到路由网络的消息。 在生成消息时，消息生成器执行与地址数据和地址转换表的内容相关的地址转换操作，以生成更新的地址数据，其使用与为消息生成地址信息相结合的数据。

公开(公告)号：US5680550A

公开(公告)日：1997-10-21

申请号：US388031

申请日：1995-02-13

申请人： Bradley C. Kuszmaul ,  Charles E. Leiserson ,  Shaw-Wen Yang ,  Carl R. Feynman ,  W. Daniel Hillis ,  David C. Douglas

发明人： Bradley C. Kuszmaul ,  Charles E. Leiserson ,  Shaw-Wen Yang ,  Carl R. Feynman ,  W. Daniel Hillis ,  David C. Douglas

IPC分类号： G06F15/16 ,  G06F11/00 ,  G06F11/08 ,  G06F11/22 ,  G06F15/173 ,  G06F15/80 ,  G06F13/00 ,  G06F3/00

CPC分类号： G06F15/17381 ,  G06F11/08 ,  G06F11/22 ,  G06F11/324 ,  G06F15/17343 ,  H04L45/48 ,  H04L49/35 ,  H04L49/555 ,  G06F2201/88

摘要： A digital computer includes a plurality of processing elements, a command processor, a diagnostic processor and a communications network. The processing elements each performs data processing and data communications operations in connection with commands. The processing elements also performing diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The command processor generates commands for the processing elements, and also performs diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The diagnostic processor generates diagnostic requests. The communication network includes three elements, including a data router, a control network and a diagnostic network. The data router is connected to the processing elements for facilitating the transfer of data among them during a data communications operation. The control network is connected to the processing elements and the command processor for transferring commands from the command processor to the processing elements. The diagnostic network connected to the processing elements, the command processor and the diagnostic processor for transferring diagnostic requests from the diagnostic processor to the processing elements and the command processor and for transferring diagnostic results from the processing elements and the command processor to the diagnostic processor.

摘要翻译： 数字计算机包括多个处理元件，命令处理器，诊断处理器和通信网络。 处理元件各自执行与命令相关的数据处理和数据通信操作。 处理元件还响应诊断操作请求执行诊断操作，并响应于此提供诊断结果。 命令处理器为处理元件生成命令，并且还响应诊断操作请求执行诊断操作并响应于此提供诊断结果。 诊断处理器产生诊断请求。 通信网络包括三个元件，包括数据路由器，控制网络和诊断网络。 数据路由器连接到处理元件，以便在数据通信操作期间便于它们之间的数据传输。 控制网络连接到处理元件和命令处理器，用于将命令从命令处理器传送到处理元件。 连接到处理元件的诊断网络，命令处理器和诊断处理器，用于将诊断请求从诊断处理器传送到处理元件和命令处理器，并将诊断结果从处理元件和命令处理器传送到诊断处理器。

公开(公告)号：US5390298A

公开(公告)日：1995-02-14

申请号：US183217

申请日：1994-01-14

申请人： Bradley C. Kuszmaul ,  Charles E. Leiserson ,  Shaw-Wen Yang ,  Carl R. Feynman ,  W. Daniel Hillis ,  David Wells ,  Cynthia J. Spiller

发明人： Bradley C. Kuszmaul ,  Charles E. Leiserson ,  Shaw-Wen Yang ,  Carl R. Feynman ,  W. Daniel Hillis ,  David Wells ,  Cynthia J. Spiller

IPC分类号： G06F15/16 ,  G06F11/00 ,  G06F11/08 ,  G06F11/22 ,  G06F15/173 ,  G06F15/80 ,  G06F13/00

CPC分类号： G06F15/17381 ,  G06F11/08 ,  G06F11/22 ,  G06F11/324 ,  G06F15/17343 ,  H04L45/48 ,  H04L49/35 ,  H04L49/555 ,  G06F2201/88

摘要： A computer including a processor array and a routing network. Processors in the processor array generate messages for transfer to over the routing network, each message including a path identifier portion identifying a path from a source, message processor to a destination processor. The routing network comprises a plurality of interconnected router nodes, at least some of said router nodes being connected to the processors to receive messages therefrom and transmit messages thereto. Each router node operates in a plurality of modes. In a first mode, the router nodes couple received messages to a router node connected thereto in accordance with the path identifier portion to thereby transfer each respective message along the path identified in its path identifier portion. In a second mode, the router node couple received messages to predetermined ones of the router nodes or processors connected thereto, the predetermined ones of said router nodes or processors being selected to facilitate transfer of a message to a nearby processor to facilitate the rapid emptying of the routing network of messages. A control element controls the router nodes to enable them to operate in the first mode or second mode generally contemporaneously.

摘要翻译： 包括处理器阵列和路由网络的计算机。 处理器阵列中的处理器产生用于通过路由网络传送的消息，每个消息包括标识从源，消息处理器到目的地处理器的路径的路径标识符部分。 路由网络包括多个互连的路由器节点，所述路由器节点中的至少一些连接到处理器以从其接收消息并向其发送消息。 每个路由器节点以多种模式操作。 在第一模式中，路由器节点根据路径标识符部分将接收到的消息耦合到与其连接的路由器节点，从而沿着其路径标识符部分中标识的路径传送每个相应的消息。 在第二模式中，路由器节点将接收到的消息耦合到连接到其上的路由器节点或处理器中的预定路由器节点，所选择的所述路由器节点或处理器中的预定路由器节点或处理器便于将消息传送到附近的处理器，以便于快速排空 消息的路由网络。 控制元件控制路由器节点，使得它们能够在第一模式或第二模式下同时运行。

公开(公告)号：US4709327A

公开(公告)日：1987-11-24

申请号：US499471

申请日：1983-05-31

申请人： W. Daniel Hillis ,  Thomas F. Knight, Jr. ,  Alan Bawden ,  Brewster L. Kahle ,  David Chapman ,  David P. Christman ,  Cliff A. Lasser ,  Carl R. Feynman

发明人： W. Daniel Hillis ,  Thomas F. Knight, Jr. ,  Alan Bawden ,  Brewster L. Kahle ,  David Chapman ,  David P. Christman ,  Cliff A. Lasser ,  Carl R. Feynman

IPC分类号： G06F15/80 ,  G06F15/16

CPC分类号： G06F15/8023

摘要： A parallel processing circuit is disclosed for use as the processor/memory in a highly parallel processor. The circuit comprises an instruction decoder that generates tables of outputs in response to instructions received at the decoder and a plurality of processor/memories each of which comprises a read/write memory and a processor for producing an output depending at least in part on data read from the memory and instruction information received at the instruction decoder. In addition, the circuit provides means for simultaneously addressing at least one cell in each read/write memory to write data thereto or read data therefrom and means for providing to each processor an output table from the decoder, the particular output table depending on instruction information received at the decoder. Further the processing circuit comprises means for selecting from the output table a particular output depending on data input to the processor. Advantageously, each processor/memory also comprises a flag controller for controlling the reading of a plurality of flags and means for simultaneously addressing each flag controller to read a flag for input into the processor associated therewith.Preferably, each processor is a bit-serial processor with three inputs, two from the read/write memory and one from the flag controller, and two outputs, one to the read/write memory and one to the flag controller; and the decoder and the plurality of processor/memories and formed on a single, integrated circuit chip.

摘要翻译： 公开了一种用于高度并行处理器中的处理器/存储器的并行处理电路。 电路包括指令解码器，其响应于在解码器处接收到的指令而生成输出表，以及多个处理器/存储器，每个处理器/存储器包括读/写存储器和用于至少部分地基于数据读取产生输出的处理器 从在指令解码器处接收的存储器和指令信息。 此外，电路提供用于同时寻址每个读/写存储器中的至少一个单元以向其中写入数据或从其读取数据的装置，用于向每个处理器提供来自解码器的输出表的装置，该特定输出表取决于指令信息 在解码器处接收。 此外，处理电路包括用于根据输入到处理器的数据从输出表选择特定输出的装置。 有利地，每个处理器/存储器还包括用于控制多个标志的读取的标志控制器和用于同时寻址每个标志控制器以读取用于输入到与其相关联的处理器的标志的装置。 优选地，每个处理器是具有三个输入的位串行处理器，两个来自读/写存储器和一个来自标志控制器的两个输出，一个输出到读/写存储器，一个输出到该标志控制器; 以及解码器和多个处理器/存储器并形成在单个集成电路芯片上。