公开(公告)号：US07093115B2

公开(公告)日：2006-08-15

申请号：US10326394

申请日：2002-12-19

申请人： David I. Poisner ,  Michael N. Derr ,  Darren Abramson ,  Zohar Bogin ,  Adit Tarmaster ,  William Knolla

发明人： David I. Poisner ,  Michael N. Derr ,  Darren Abramson ,  Zohar Bogin ,  Adit Tarmaster ,  William Knolla

IPC分类号： G06F15/177 ,  G06F11/22

CPC分类号： G06F9/4403

摘要： Embodiments of the present invention provide a method and apparatus for detecting an interruption in memory initialization. A status bit for indicating whether memory initialization was interrupted or not is stored in a register. A basic input/output system (BIOS) sets the status bit prior to initialization and clears the status bit after initialization. The status bit cannot be reset by a standard platform reset. In operation, as the system is reset or turned on and prior to initialization, the BIOS checks the status bit to detect possible improper memory initialization. When the status bit is set, the BIOS concludes that a memory initialization had not completed and thus might be incorrect. The BIOS then causes power to be cycled to memory and any other steps needed are taken to return the memory to a functional state.

摘要翻译： 本发明的实施例提供了一种用于检测存储器初始化中的中断的方法和装置。 用于指示存储器初始化是否中断的状态位是否存储在寄存器中。 基本输入/输出系统（BIOS）在初始化之前设置状态位，并在初始化后清除状态位。 状态位不能通过标准平台复位来复位。 在操作中，当系统复位或打开和初始化之前，BIOS检查状态位以检测可能的不正确的存储器初始化。 当状态位置位时，BIOS得出结论：存储器初始化尚未完成，因此可能不正确。 BIOS然后使电源循环到存储器，并且采取任何其他步骤来将存储器返回到功能状态。

公开(公告)号：US08463968B2

公开(公告)日：2013-06-11

申请号：US11096941

申请日：2005-03-31

申请人： Amir Zinaty ,  Adit Tarmaster ,  Michael Derr ,  Haim Lustig

发明人： Amir Zinaty ,  Adit Tarmaster ,  Michael Derr ,  Haim Lustig

IPC分类号： G06F13/00 ,  G06F13/36 ,  G06F13/362

CPC分类号： G06F13/4291

摘要： According to one embodiment, a computer system is disclosed. The computer system includes a flash memory device, a serial peripheral interface (SPI) coupled to the flash memory device, a network controller coupled to the SPI; and a chipset coupled to the SPI. The chipset includes an arbiter to arbitrate between the network controller and the chipset for control of the SPI to access the flash memory device.

摘要翻译： 根据一个实施例，公开了一种计算机系统。 计算机系统包括闪速存储器件，耦合到闪存器件的串行外设接口（SPI），耦合到SPI的网络控制器; 以及耦合到SPI的芯片组。 芯片组包括仲裁器，用于在网络控制器和芯片组之间进行仲裁，以控制SPI以访问闪存设备。

公开(公告)号：US20060224803A1

公开(公告)日：2006-10-05

申请号：US11096941

申请日：2005-03-31

申请人： Amir Zinaty ,  Adit Tarmaster ,  Michael Derr ,  Haim Lustig

发明人： Amir Zinaty ,  Adit Tarmaster ,  Michael Derr ,  Haim Lustig

IPC分类号： G06F13/00

CPC分类号： G06F13/4291

摘要： According to one embodiment, a computer system is disclosed. The computer system includes a flash memory device, a serial peripheral interface (SPI) coupled to the flash memory device, a network controller coupled to the SPI; and a chipset coupled to the SPI. The chipset includes an arbiter to arbitrate between the network controller and the chipset for control of the SPI to access the flash memory device.