公开(公告)号：US07900072B2

公开(公告)日：2011-03-01

申请号：US11963215

申请日：2007-12-21

Applicant: Michael Berger ,  Michael Derr ,  Joshua Resch ,  Mukesh Kataria ,  Mazen Gedeon ,  Eli Kupermann ,  Jeffrey John Vick

Inventor： Michael Berger ,  Michael Derr ,  Joshua Resch ,  Mukesh Kataria ,  Mazen Gedeon ,  Eli Kupermann ,  Jeffrey John Vick

IPC: G06F1/00 ,  G06F1/26 ,  H04M1/00 ,  G11C5/14

CPC classification number: G06F1/3203 ,  G06F1/3243 ,  Y02D10/152

Abstract: Various embodiments are directed to a tri-layered power scheme for architectures which contain a microcontroller. In one embodiment, a power management system may comprise a microcontroller in a chipset, a low consumption power well to control a power supply to the microcontroller, and a power controller to control a power supply to the low consumption power well. The power management system may be arranged to switch among multiple power consumption states. In a maximum power consumption state, the microcontroller is on, the power controller is on, and the low consumption power well is on. In an intermediate power consumption state, the microcontroller is off, the power controller is on, and the low consumption power well is required to be on. In a minimum power consumption state, the microcontroller is off, the power controller is on, and the low consumption power well is optionally on or off at the discretion of the power controller. Other embodiments are described and claimed.

Abstract translation: 各种实施例针对包含微控制器的架构的三层电力方案。 在一个实施例中，电源管理系统可以包括芯片组中的微控制器，以及用于控制对微控制器的电源的低功耗电力，以及功率控制器以便很好地控制对低功耗电力的供电。 电源管理系统可以被布置成在多个功耗状态之间切换。 在最大功耗状态下，微控制器打开，电源控制器打开，低功耗电源正常。 在中间功耗状态下，微控制器关闭，电源控制器处于打开状态，低功耗电源需要打开。 在最小功耗状态下，微控制器处于关闭状态，功率控制器处于开启状态，低功耗状态可以根据电源控制器选择开启或关闭。 描述和要求保护其他实施例。

公开(公告)号：US20060200690A1

公开(公告)日：2006-09-07

申请号：US11074233

申请日：2005-03-05

Applicant: Leslie Cline ,  Siripong Sritanyaratana ,  Alon Naveh ,  Shai Rotem ,  Eric Samson ,  Michael Derr

Inventor： Leslie Cline ,  Siripong Sritanyaratana ,  Alon Naveh ,  Shai Rotem ,  Eric Samson ,  Michael Derr

IPC: G06F1/32

CPC classification number: G06F12/0835 ,  G06F2212/1028 ,  Y02D10/13

Abstract: Systems and methods of managing power provide for placing a processor in a non-snoopable state, where the processor is associated with a system memory. One or more data transfers between a controller and the system memory can be serviced while the processor is in the non-snoopable state. In one embodiment, it is determined that the processor has flushed an internal cache of the processor to the system memory before placing the processor in the non-snoopable state.

公开(公告)号：US20050223292A1

公开(公告)日：2005-10-06

申请号：US10781371

申请日：2004-02-17

Applicant: Chee Lee ,  Vui Liew ,  Mikal Hunsaker ,  Michael Derr

Inventor： Chee Lee ,  Vui Liew ,  Mikal Hunsaker ,  Michael Derr

IPC: G06F11/00

CPC classification number: G06F8/60

Abstract: A patch mechanism is described, which can be used to detect and workaround defects and conditions existing in an integrated circuit chip. The patch mechanism includes a trigger-matching logic incorporated within an integrated circuit chip to capture an incoming request cycle and determine if the captured incoming cycle matches one or more of trigger conditions. The patch mechanism further includes a control logic coupled to the trigger-matching logic to select a set of instructions upon detection of at least one matched trigger condition and to execute operations corresponding to the selected set of instructions. The control logic is configured to select the set of instructions based on the at least one matched trigger condition.

Abstract translation: 描述了一种补丁机制，可用于检测和解决集成电路芯片中存在的缺陷和状况。 补丁机制包括一个集成在集成电路芯片内的触发器匹配逻辑，以捕获进入的请求周期并确定捕获的进入周期是否匹配一个或多个触发条件。 补丁机制还包括耦合到触发匹配逻辑的控制逻辑，以在检测到至少一个匹配的触发条件时选择一组指令，并执行与所选指令集相对应的操作。 所述控制逻辑被配置为基于所述至少一个匹配的触发条件来选择所述指令集。

公开(公告)号：US20070033311A1

公开(公告)日：2007-02-08

申请号：US11187712

申请日：2005-07-22

Applicant: David Young ,  Michael Derr

Inventor： David Young ,  Michael Derr

IPC: G06F13/00

CPC classification number: G06F21/57 ,  G06F13/1668

Abstract: Embodiments of the invention are generally directed to a methods, apparatuses, and systems for quiescing a processor bus agent. In one embodiment, a processor initiates the establishment of a protected domain for a computing system. A processor bus agent coupled with the processor is quiesed to reduce the potential for interference with the establishment of the protected domain. Other embodiments are described and claimed.

Abstract translation: 本发明的实施例通常涉及用于使处理器总线代理静止的方法，装置和系统。 在一个实施例中，处理器启动用于计算系统的受保护域的建立。 与处理器耦合的处理器总线代理被停顿以减少对建立受保护域的干扰的可能性。 描述和要求保护其他实施例。

公开(公告)号：US20060224803A1

公开(公告)日：2006-10-05

申请号：US11096941

申请日：2005-03-31

Applicant: Amir Zinaty ,  Adit Tarmaster ,  Michael Derr ,  Haim Lustig

Inventor： Amir Zinaty ,  Adit Tarmaster ,  Michael Derr ,  Haim Lustig

IPC: G06F13/00

CPC classification number: G06F13/4291

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a flash memory device, a serial peripheral interface (SPI) coupled to the flash memory device, a network controller coupled to the SPI; and a chipset coupled to the SPI. The chipset includes an arbiter to arbitrate between the network controller and the chipset for control of the SPI to access the flash memory device.

公开(公告)号：US20050182869A1

公开(公告)日：2005-08-18

申请号：US10781512

申请日：2004-02-17

Applicant: Chee Lee ,  Vui Liew ,  Mikal Hunsaker ,  Michael Derr

Inventor： Chee Lee ,  Vui Liew ,  Mikal Hunsaker ,  Michael Derr

IPC: G06F3/00

CPC classification number: G06F12/0638

Abstract: A system is described for providing a patch mechanism within an input/output (I/O) controller, which can be used to workaround defects and conditions existing in the I/O controller. The system includes a patch module coupled to a completion queue included in the I/O controller. The patch module is used to sample incoming cycles received by the I/O controller and to determine if the captured incoming cycle matches one or more of preprogrammed trigger conditions. The patch module is capable of working around a captured non-posted request cycle by controlling header information loaded into the completion queue and by instructing the completion queue whether or not to discard a completion received from a designated end-device.

Abstract translation: 描述了一种系统，用于在输入/输出（I / O）控制器内提供补丁机制，可用于解决I / O控制器中存在的缺陷和状况。 该系统包括耦合到包括在I / O控制器中的完成队列的补丁模块。 补丁模块用于对I / O控制器接收的进入周期进行采样，并确定捕获的进入周期是否匹配一个或多个预编程触发条件。 补丁模块能够通过控制加载到完成队列中的头信息并通过指示完成队列来确定是否丢弃从指定的终端设备接收到的完成，来围绕捕获的非发布请求周期进行操作。

公开(公告)号：US5860112A

公开(公告)日：1999-01-12

申请号：US579116

申请日：1995-12-27

Applicant: Brian K. Langendorf ,  Michael Derr

Inventor： Brian K. Langendorf ,  Michael Derr

IPC: G06F12/08

CPC classification number: G06F12/0804

Abstract: Apparatus and a method for utilizing a memory bus write buffer to blend up-to-date data stored in a processor cache and being written back to memory with data in the write buffer being written to the same memory address by a bus master in order to maintain data coherency. The circuitry also utilizes the memory bus write buffer to write valid data furnished in a bus master write over up-to-date data in the write buffer being written to the same memory address from a processor cache in order to maintain data coherency. Combining the data from the two sources prior to writing it to memory eliminates at least one write operation by the write controller along with any associated ECC value generation, may eliminate a number of read/modify/write back operations with any associated ECC value generations, and can double the effective depth of the buffer.

Abstract translation: 一种用于利用存储器总线写入缓冲器来混合存储在处理器高速缓存中的最新数据并被写回到存储器的方法，其中写入缓冲器中的数据被总线主机写入相同的存储器地址，以便 维护数据一致性。 该电路还利用存储器总线写入缓冲器来写入在总线主机中提供的有效数据，写入缓冲器中的最新数据被写入来自处理器高速缓存的相同存储器地址，以便保持数据一致性。 在写入存储器之前将来自两个源的数据组合，消除了写入控制器至少一次写入操作以及任何相关联的ECC值生成，可以消除与任何相关联的ECC值代的多个读取/修改/回写操作， 并可以将缓冲区的有效深度加倍。

公开(公告)号：US20070233909A1

公开(公告)日：2007-10-04

申请号：US11395678

申请日：2006-03-30

Applicant: Michael Derr ,  Darren Abramson ,  Bryan Doucette ,  Karthi Vadivelu

Inventor： Michael Derr ,  Darren Abramson ,  Bryan Doucette ,  Karthi Vadivelu

IPC: G06F3/00 ,  G06F13/14

CPC classification number: G06F1/3203 ,  G06F1/3253 ,  Y02D10/151 ,  Y02D50/20

Abstract: A method, apparatus, and system to synchronize multiple host controllers with non-uniform frame rates. The apparatus includes a first host controller, a second host controller, and logic. The first host controller is configured to access memory at a first frame rate. The second host controller is configured to access the memory at a second frame rate which is different from the first frame rate. The logic is coupled to the first and second host controllers to synchronize the memory accesses of the first and second host controllers at a common frame rate. Other embodiments are described.

Abstract translation: 一种以非均匀帧速率同步多个主机控制器的方法，装置和系统。 该装置包括第一主机控制器，第二主机控制器和逻辑。 第一主机控制器被配置为以第一帧速率访问存储器。 第二主机控制器被配置为以与第一帧速率不同的第二帧速率访问存储器。 该逻辑耦合到第一和第二主机控制器以以公共帧速率同步第一和第二主机控制器的存储器访问。 描述其他实施例。

公开(公告)号：US08463968B2

公开(公告)日：2013-06-11

申请号：US11096941

申请日：2005-03-31

Applicant: Amir Zinaty ,  Adit Tarmaster ,  Michael Derr ,  Haim Lustig

Inventor： Amir Zinaty ,  Adit Tarmaster ,  Michael Derr ,  Haim Lustig

IPC: G06F13/00 ,  G06F13/36 ,  G06F13/362

CPC classification number: G06F13/4291

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a flash memory device, a serial peripheral interface (SPI) coupled to the flash memory device, a network controller coupled to the SPI; and a chipset coupled to the SPI. The chipset includes an arbiter to arbitrate between the network controller and the chipset for control of the SPI to access the flash memory device.

Abstract translation: 根据一个实施例，公开了一种计算机系统。 计算机系统包括闪速存储器件，耦合到闪存器件的串行外设接口（SPI），耦合到SPI的网络控制器; 以及耦合到SPI的芯片组。 芯片组包括仲裁器，用于在网络控制器和芯片组之间进行仲裁，以控制SPI以访问闪存设备。

公开(公告)号：US5889968A

公开(公告)日：1999-03-30

申请号：US939801

申请日：1997-09-30

Applicant: Joseph A. Bennett ,  Darren Abramson ,  Michael Derr ,  Zohar Bogin

Inventor： Joseph A. Bennett ,  Darren Abramson ,  Michael Derr ,  Zohar Bogin

IPC: G06F13/36 ,  G06F13/14

CPC classification number: G06F13/36

Abstract: A method and apparatus is disclosed for providing an interlocked broadcast message that solves the problem of a system component taking action in response to a broadcast message issued by a processor before the processor receives communication that the broadcast message has been delivered. A broadcast message transaction request is issued from a processor. The broadcast message transaction request is posted in a transaction request buffer. A reply is communicated to the processor that the broadcast message transaction request has been posted, and the broadcast message is then delivered over the bus. In an alternative embodiment, after the broadcast message transaction request is issued from the processor, the broadcast message transaction request is stored in a transaction request buffer. The broadcast message is only delivered over the bus once it has been determined that the reply to the processor that the broadcast message transaction has completed can be immediately delivered to the processor following the delivery of the broadcast message.

Abstract translation: 公开了一种用于提供互锁广播消息的方法和装置，其解决了在处理器接收到广播消息已被传送的通信之前响应于由处理器发出的广播消息而采取动作的系统组件的问题。 从处理器发出广播消息交易请求。 广播消息事务请求被发布在事务请求缓冲器中。 向处理器传送广播消息交易请求已经被发布的答复，然后通过总线传送广播消息。 在替代实施例中，在从处理器发出广播消息事务请求之后，广播消息事务请求被存储在事务请求缓冲器中。 一旦确定广播消息交易已经完成的对处理器的答复可以在传送广播消息之后立即传送到处理器，广播消息仅在总线上传送。